Transaction Termination - Freescale Semiconductor MSC8144E Reference Manual

PCI
PCI_CLK
PCI_AD[31–0]
PCI_C/BE[3–0]
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
A write transaction is similar to a read transaction except no turnaround cycle is needed following
the address phase because the initiator provides both address and data. Data phases are the same
for both read and write transactions.

15.1.8.2 Transaction Termination

The termination of a PCI transaction is orderly and systematic, regardless of the cause of the
termination. All transactions end when
the idle cycle.
The VCOP as an initiator terminates a transaction when
asserted. This indicates that the final data phase is in progress. The final data transfer occurs
when both and
PCI_TRDY
initiator initiated termination. If the VCOP detects that
more than four clocks after the assertion of
next clock, deasserts
PCI_IRDY
lost on aborted writes.
When the VCOP as a target needs to suspend a transaction, it asserts
remains asserted until
PCI_STOP
may or may not be transferred during the request for termination. If
asserted during the assertion of
termination is called a disconnect B, shown in Figure 15-5. If
is asserted but
PCI_STOP
asserted and the data is transferred. This is called a "disconnect A" target-initiated termination,
also shown in Figure 15-5. However, if
more data is transferred, and the initiator therefore does not have to wait for a final data transfer
(see the retry diagram in Figure 15-5).
15-8
ADDR DATA1 DATA2
CMD BEs 1
Figure 15-4. Burst Write Example
PCI_FRAME
are asserted. An initiator-abort is an abnormal case of an
PCI_IRDY
PCI_FRAME
. On aborted reads, the VCOP returns 0xFFFF_FFFF. The data is
is deasserted. Depending on the circumstances, data
PCI_FRAME
, data is transferred. This type of target-initiated
PCI_STOP
is not,
PCI_IRDY PCI_TRDY
PCI_TRDY
MSC8144E Reference Manual, Rev. 3
DATA3 DATA4
BEs 2 BEs 3 BEs 4
and are both deasserted, indicating
PCI_IRDY
is deasserted and
PCI_FRAME
has remained deasserted for
PCI_DEVSEL
, it deasserts
PCI_FRAME
PCI_STOP
PCI_TRDY
PCI_TRDY
must remain asserted until
is deasserted when
PCI_IRDY
and then, on the
. Once asserted,
and are
PCI_IRDY
is asserted when
is
PCI_IRDY
is asserted, no
PCI_STOP
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is