Bus Transactions - Freescale Semiconductor MSC8144E Reference Manual

PCI

15.1.8 Bus Transactions

The timing diagrams in this section show the relationship of significant signals involved in bus
transactions.
Note the following conventions:
When a signal is drawn as a solid line, it is actively being driven by the current initiator or
target.
When a signal is drawn as a dashed line, no agent is actively driving it.
Three-stated signals with slashes between the two rails have indeterminate values.
The terms edge and clock edge refer to the rising edge of the clock.
The terms asserted and deasserted refer to the globally visible state of the signal on the
clock edge, and not to signal transitions.
The symbol
15.1.8.1 Read and Write Transactions
Both read and write transactions begin with an address phase followed by a data phase. The
address phase occurs when
contain a byte address and the
consists of the actual data transfer and possible wait cycles; the byte enable signals remain
actively driven from the first clock of the data phase through the end of the data transfer.
A read transaction starts when
signals indicate a read command. Figure 15-1 shows an example of a single beat read
transaction.
PCI_CLK
PCI_AD[31–0]
PCI_C/BE[3–0]
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
Figure 15-2 shows an example of a burst read transaction.
15-6
represents a turnaround-cycle.
is asserted for the first time, and the
PCI_FRAME
signals contain a bus command. The data phase
PCI_C/BE[3–0]
is asserted for the first time and the
PCI_FRAME
ADDR
CMD
Figure 15-1. Single Beat Read Example
MSC8144E Reference Manual, Rev. 3
BYTE ENABLES
signals
AD[31–0]
PCI_C/BE[3–0]
DATA
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