Restrictions - Freescale Semiconductor MSC8144E Reference Manual

Table 13-4. MSC8144E Interrupt Table (Continued)
Channel 0 Interrupt
Channel 1 Interrupt
Channel 2 Interrupt
Channel 3 Interrupt
General Hardware Interrupt
13.4

Restrictions

Some interrupts can cause the core to deadlock. These interrupts can occur when the core issues a
single read towards a peripheral and the read triggers an interrupt. The deadlock occurs because
the interrupt signal reaches the core before the actual data. As a result, the core jumps to the
interrupt handler and upon returning from handling the interrupt, reissues the read request.
Table 13-5 summarizes the problematic scenarios and resulting restrictions on the user.
EPIC Index
226 IRQ0
227 IRQ1
228 IRQ2
229 IRQ3
230 IRQ4
231 IRQ5
232 IRQ6
233 IRQ7
234
IRQ8
235 IRQ9
236 IRQ10
237 IRQ11
238 IRQ12
239 IRQ13
240
IRQ14
241 IRQ15
242 NMI
Freescale Semiconductor
Interrupt Description
OCN DMA
Table 13-5. Restrictions Listed by Interrupt Source
Event Problematic scenario
External source generates a
IRQ/NMI as a response to a Core
read access from the DDR/PCI
MSC8144E Reference Manual, Rev. 3
Restrictions
IRQ
Level Edge
index
248 +
249 +
250 +
251 +
252 +
Restriction
The peripheral must not generate
IRQ/NMI as a response to a Core
read access from the DDR/PCI
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13-11