General Interrupt Register 1 (Gir1); General Interrupt Register 1 (Gier1_X) - Freescale Semiconductor MSC8144E Reference Manual

Quad core media signal processor
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General Configuration Registers
Name
Reset
UCC1RCLKID
9–8
UCC1TCLKID
7–6
UCC1CLKOD
5–4
UCC1RXDD
3–2
UCC1TXDD
1–0

8.2.12 General Interrupt Register 1 (GIR1)

GIR1
Bit
31
30
Type
Reset
0
0
Bit
23
22
Type
Reset
0
0
Bit
15
14
Type
Reset
0
0
Bit
7
6
Type
Reset
0
0
8-14
Table 8-11. GCR4 Bit Descriptions (Continued)
Description
0
UCC1 RX Clock In Delay
Adds a delay to the specified signal.
0
UCC1 TX Clock In Delay
Adds a delay to the specified signal.
0
UCC1 Clock Out Delay
Adds a delay to the specified signal.
0
UCC1 RX Data Delay
Adds a delay to the specified signal.
0
UCC1 TX Data Delay
Adds a delay to the specified signal.
General Interrupt Register 1
29
28
0
0
21
20
0
0
13
12
0
0
5
4
0
0
MSC8144E Reference Manual, Rev. 3
00 No delay.
01 One delay unit.
10 Two delay units.
11 Three delay units.
00 No delay.
01 One delay unit.
10 Two delay units.
11 Three delay units.
00 No delay.
01 One delay unit.
10 Two delay units.
11 Three delay units.
00 No delay.
01 One delay unit.
10 Two delay units.
11 Three delay units.
00 No delay.
01 One delay unit.
10 Two delay units.
11 Three delay units.
27
26
R/W
0
0
19
18
R/W
0
0
11
10
VNMI_3
VNMI_2
R/W
0
0
3
2
M2_3_ECC
M2_2_ECC
R/W
0
0
Settings
Offset 0x40
25
24
0
0
17
16
0
0
9
8
VNMI_1
VNMI_0
0
0
1
0
M2_1_ECC
M2_0_ECC
0
0
Freescale Semiconductor

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