Outbound Message X Descriptor Queue Dequeue Pointer Address; Registers (Omxdqdpar) - Freescale Semiconductor MSC8144E Reference Manual

16.6.62 Outbound Message x Descriptor Queue Dequeue Pointer Address

Registers (OMxDQDPAR)

OM[0–1]DQDPAR
Bit 31 30 29
TYPE
RESET 0 0 0
Bit 15 14 13
TYPE
RESET 0 0 0
OMxDQDPAR contain the address of the first descriptor in memory to be processed. Software
must initialize this register to point to the first descriptor in memory. After the descriptor is
processed, the message unit controller increments the outbound message descriptor queue
dequeue pointer address in OMxDQDPAR to point to the next descriptor. If the outbound
message descriptor queue enqueue pointer and the outbound message descriptor queue dequeue
pointer are not equal (indicating that the queue is not empty), the message unit controller reads
the next descriptor from memory for processing. If the enqueue and dequeue pointers are equal
after the message unit controller increments the dequeue pointer, the queue is empty and the
message unit halts until the processor increments the enqueue pointer. Incrementing the pointer
indicates that a new descriptor was added to the queue and is ready for processing. If the queue
becomes empty and OMxMR[QEIE] is set, OMxSR[QEI] is set and an interrupt is generated.
When software initializes these registers, they must be aligned on a boundary equal to the number
of queue entries × 32 bytes (the size of each queue descriptor).For example, if there are eight
entries in the queue, the register must be 256-byte aligned. The number of queue entries is set in
OMnMR[CIRQ_SIZ].
Bits Reset
DQDPA 0
31–5
— 0
4–0
Freescale Semiconductor
Outbound Message 0–1 Descriptor
Queue Dequeue Pointer Address Registers
28 27 26 25
0 0 0 0
12 11 10 9
DQDPA
R/W
0 0 0 0
Table 16-105. OMxDQDPAR Field Descriptions
Descriptor Dequeue Pointer Address
Contains the address of the first descriptor in memory to process. The descriptor must be aligned
to a 32-byte boundary. For proper operation, this field should be modified only when the
outbound message controller is not enabled.
Reserved. Write to zero for future compatibility.
MSC8144E Reference Manual, Rev. 3
24 23 22 21
DQDPA
R/W
0 0 0 0
8 7 6 5
0 0 0 0
Description
RapidIO Programming Model
Offset 0x1300C + x*0x100
20 19 18 17
0 0 0 0
4 3 2 1
—
R
0 0 0 0
16
0
0
0
16-171