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20.6.4 SCI Data Register (SCIDR)
SCIDR
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
R8
T8
Type
R
R/W
Reset
0
0
0
Note:
In the SCIDR, writing affects only T[8–0]; writing to R[8–0] has no effect.
Name
—
31–16
R8
15
T8
14
—
13–8
7–0
R[7–0]
T[7–0]
Notes: 1.
If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten. The same value
is transmitted until T8 is rewritten.
2.
In 8-bit data format, only SCIDR[7–9] need to be accessed.
3.
When transmitting in 9-bit data format, write to SCIDR[15–0] (one access). Otherwise, write first to T8 and then
to the low byte (SCIDR[7–0]).
Freescale Semiconductor
SCI Data Register
28
27
26
25
0
0
0
0
12
11
10
9
—
R/W
0
0
0
0
Table 20-12. SCIDR Bit Descriptions
Reset
Description
0
Reserved. Write to zero for future compatibility.
0
Received Bit 8
The ninth data bit received when the SCI is
configured for 9-bit data format (M = 1).
0
Transmit Bit 8
The ninth data bit transmitted when the SCI is
configured for 9-bit data format (M = 1).
0
Reserved. Write to zero for future compatibility.
0
Received Bits 7–0
Received bits seven through zero for 9-bit or
8-bit data formats.
Transmit Bits 7–0
Transmit bits seven through zero for 9-bit or
8-bit formats.
MSC8144E Reference Manual, Rev. 3
24
23
22
21
—
R/W
0
0
0
0
8
7
6
5
R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
0
0
0
0
UART Programming Model
Offset 0x18
20
19
18
17
0
0
0
0
4
3
2
1
R[7–0] is R
T[7–0] is W
0
0
0
0
Settings
16
0
0
0
20-31
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