Instruction Decoding - Freescale Semiconductor MSC8144E Reference Manual

25.1.3 Instruction Decoding

The MSC8144E includes the three mandatory public instructions EXTEST,
SAMPLE/PRELOAD, and BYPASS and also supports the optional CLAMP and HIGHZ
instructions defined by IEEE Std. 1149.1. The following public instructions perform key
functions:
READ_STATUS enables the JTAG port to query the status of the OCE circuitry.
ENABLE_ONCE enables the JTAG port to communicate with the OCE circuitry.
DEBUG_REQUEST enables the JTAG port to force the MSC8144E into Debug mode.
CHOOSE_ONCE allows the operation of multiple OCE devices. This instruction should
always execute before the first ENABLE_ONCE instruction and should shift a 1 to the
SC3400 OCE module choose cells for each module that you want to enable. Since there
are four internal OCE modules, you must shift 4 bits to the choose cells. For details, see
Section 25.1.4.
The MSC8144E includes an 8-bit instruction register without parity, consisting of a shift register
with eight parallel outputs. Data is transferred from the shift register to the parallel outputs during
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the controller state. The eight bits decode to the unique instructions listed in Table
UPDATE IR
25-3. All other encoding, with the exception of the manufacturer private instructions, is reserved
for future enhancements and is decoded as BYPASS.
The parallel output of the Instruction Register is reset to 0xF3 in the test-logic-reset controller
state, which is equivalent to the IDCODE instruction. During the
parallel inputs to the instruction shift register are loaded with the code 01 in the least significant
bits, as required by the standard. Two bits of the GPR are configured to select an SC3400 core,
whose status is output from the multiplexer. Therefore, the status of all SC3400 cores can be
viewed serially by updating the GPR between each SC3400 core status reading. Alternatively, all
four SC3400 cores can be viewed simultaneously from the PIREG. For details on core states,
refer to the SC3000-Family Processor Core Reference Manual.
Table 25-2. Instruction Register Capture and SC3400 Core Status Values
Name/bits
FBiST_Done FBIST Done
7 Field built-in self test completed.
MBIST_Failed MBIST Failed
6 Indicates an MBIST failure.
MBIST_Done MBIST Done
5 Indicates that the MBIST is completed.
— Reserved. Always 0.
4
Freescale Semiconductor
Description
MSC8144E Reference Manual, Rev. 3
TAP, Boundary Scan, and OCE
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controller state, the
CAPTURE IR
Settings
0 FBIST not complete.
1 FBIST completed
0 No MBIST failure.
1 MBIST failed
0 Either an activated MBIST is still running or
no MBIST was initiated by the last HRESET
1 All active MBISTs are complete
25-5