Table of Contents
Advertisement
PCI
15.2.2.11 Header Type Configuration Register (HTCR)
HTCR
Bit
7
6
Type
Reset
0
0
HTCR specifies the header type and is hard-wired to 0x00.
15.2.2.12 BIST Control Configuration Register (BISTCCR)
BISTCCR
Bit
7
6
Type
Reset
0
0
BISTCCR specifies the BIST control and is hard-wired to 0x00.
15.2.2.13 PIMMR Base Address Configuration Register (PIMMRBACR)
PIMMRBACR
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
Type
R/W
Reset
0
0
0
The PIMMRBACR is provided to allow access to local memory mapped registers. The Window
size and translation are hard-wired and define a 32 Mbyte address space starting at address
0xFE000000 in the local memory space. Table 15-15 shows the PIMMRBACR bit fields.
Bits
BA
Base Address
31–4
This field defines the low portion of the base address for the internal memory-mapped register space.
PRE
Prefetchable
3
This read-only bit is hardwired internally to 0.
T
Type
2–1
Hard-wired internally to 00.
MSI
Memory Space Indicator
0
Hard-wired internally to 0.
15-28
Header Type Configuration Register
5
4
0
0
BIST Control Configuration Register
5
4
0
0
PIMMR Base Address Configuration Register
28
27
26
25
0
0
0
0
12
11
10
9
BA
0
0
0
0
Table 15-15. PIMMARBACR Field Descriptions
MSC8144E Reference Manual, Rev. 3
3
2
HT
R
0
0
3
2
BIST_CTL
R
0
0
24
23
22
21
BA
R/W
0
0
0
0
8
7
6
5
R
0
0
0
0
Description
Offset 0x0E
1
0
0
0
Offset 0x0F
1
0
0
0
Offset 0x10
20
19
18
17
0
0
0
0
4
3
2
1
PRE
T
0
0
0
0
Freescale Semiconductor
16
0
0
MSI
0
Advertisement
Table of Contents
