L2 Icache Global Invalidation Command - Freescale Semiconductor MSC8144E Reference Manual

Note: Port 2 of the CLASS initiator is disabled at reset and must not be enabled by the user
(otherwise the interleaving between the two banks will not work).
Do not disable the cache memory modules after they are enabled. To disable L2
ICache operation, disable the L2 Cache window by clearing the L2IC_CEN[DEN] bit
and then write start and end addresses of 0x000000 to L2IC_CSA and L2IC_CEA.
If the cache is disabled after initialization, you must set the L2IC_CR2[CE] bit before
setting the L2IC_CEN[DEN] bit to enable the cache.

11.4.6.2 L2 ICache Global Invalidation Command

The L2 ICache global invalidation command clears the valid bits in both cache modules in a
single clock cycle. To execute a global invalidate, enter the sweep/invalidate command in the CC
field and set the CGS bit in of L2IC_CR1 (see Section 11.8.2). The command also resets the
PLRU machine.
11.4.6.3 L2 ICache Global Lock Mode
To enter global lock mode, set the L2IC_CR2[CGL] bit (see Section 11.8.3). When globally
locked, new data fetches are not written to the L2 ICache and no lines are trashed. Hit accesses
are served as usual. Miss accesses are served without updating the cache memory. The PLRU
machine is not updated while the L2 ICache is locked. The L2 ICache Global Lock mode may be
useful to improve the performance of some applications that may be sensitive to interrupts, for
example. After asserting this mode, all open miss accesses are served and updated as if L2 ICache
is not globally locked. The lock mode disables only new miss data updates that are initiated after
the L2 ICache enters global lock mode.
The sweep operation overrides the global lock status. The value of the global lock bit is ignored
during the cache sweep operation.
11.4.6.4 L2 ICache Partial Lock
L2 ICache can be partially locked to protect certain data. The lock is done in line resolution (16
VBRs). The replace mechanisms are disabled for data that does not correlate with the active
cache lock boundaries. In case of TAG match, the data of a locked line can be updated with new
fetches to this line, but L2 ICache lines are not replaced. The locking is done in way boundaries.
The reduced open boundaries contain 2 or 4 ways.
The exact partial lock configuration is programmed via dedicated register.
Freescale Semiconductor
MSC8144E Reference Manual, Rev. 3
L2 Instruction Cache
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