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7.2 TAP CONTROLLER
The TAP controller is responsible for interpreting the sequence of logical values on the
TMS signal. It is a synchronous state machine that controls the operation of the JTAG
logic. The state machine is shown in Figure 7-2; the value shown adjacent to each arc
represents the value of the TMS signal sampled on the rising edge of the TCK signal. For
a description of the TAP controller states, please refer to the IEEE 1149.1 document.
TEST LOGIC
1
RESET
RUN-TEST/IDLE
0
7.3 BOUNDARY SCAN REGISTER
The MC68306 IEEE 1149.1 implementation has a 124-bit boundary scan register. This
register contains bits for all device signal and clock pins and associated control signals.
MOTOROLA
0
1
SELECT-DR_SCAN
1
CAPTURE-DR
0
UPDATE-DR
1
Figure 7-2. TAP Controller State Machine
MC68306 USER'S MANUAL
1
0
0
0
SHIFT-DR
1
1
EXIT1-DR
0
0
PAUSE-DR
1
0
EXIT2-DR
1
0
1
SELECT-IR_SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
0
1
1
EXIT1-IR
0
0
PAUSE-IR
1
EXIT2-IR
1
UPDATE -IR
1
0
7-3
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