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CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
12.5.1 Operation of free-running timer
This section explains the operation and timing of the free-running timer.
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Operation of free-running timer
The free-running timer starts counting at a counter value of "0000" after clearing reset operation.
This counter value is used as a reference time for output compare and input capture.
The count value is cleared under the following conditions:
•
Overflow occurs
•
Compare match is found with the output compare value 0 (mode setting is required)
•
SCLR bit of TCCS register is set to "1"
•
TCDT register is set to "0000"
•
Reset occurs
An interrupt occurs if an overflow is generated or the counter value of free-running timer the
value of compare register 0 matches compare results (a compare results match interrupt
requires mode setting).
Figure 12.5-1 shows the timing chart of the counter cleared because of an overflow. Figure
12.5-2 shows the timing chart of the counter cleared because of a compare results match.
Figure 12.5-1 Timing chart of counter cleared because of overflow
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Interrupt
238
Time
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