Fig. 2.11 Ports 00 To 07 And 10 To 13 - Fujitsu MB89140 Series Hardware Manual

I/O PORTS
Internal data bus
PDR
PDR read
PDR read
(when Read Modify Write instruction executed)
PDR write
DDR write
HARDWARE CONFIGURATION
Analog input
When using as an analog input, set 0 at the DDR to turn off the output tran-
sistor. If the bits of the PCR0 and PCR1 registers corresponding to the
ports to be used as analog inputs are 1, write 0 at these registers to inhibit
use as general-purpose input ports. At this time, 0 is always read even if
the value of each port is read (input ports cannot be read).
A/D converter
Output latch
DDR
Stop mode (SPL = 1)

Fig. 2.11 Ports 00 to 07 and 10 to 13

(2) P14 to P16: CMOS-type I/O ports
Switching input and output
These ports have a data-direction register (DDR) and port-data register
(PDR) for each bit. Input and output can be set independently for each
bit. The pin with the DDR set to 1 is set to output, and the pin with the DDR
set to 0 is set to input.
Operation for output port (DDR = 1)
The value written at the PDR is output to the pin when the DDR is set to 1.
When the PDR is read, usually, the value of the pin is read instead of the
contents of the output latch. However, when the Read Modify Write
instruction is executed, the contents of the output latch are read irrespec-
tive of the DDR setting conditions. Therefore, the bit-processing instruc-
tion can be used even if input and output are mixed with each other. When
data is written to the PDR, the written data is held in the output latch irre-
spective of the DDR setting conditions.
Operation for input port (DDR = 0)
When settings the input, the output impedance goes High. Therefore,
when the PDR is read, the value of the pin is read.
State when reset
The DDR is initialized to 0 by resetting and the output impedance goes
High at all bits. The PDR is not initialized by resetting. Therefore, set the
value of the PDR before setting the DDR to output.
2-28
Input buffer (hysteresis)
Output buffer
A/D channel select
(sampling only)
Set values of PCR0
and PCR1 registers
(default: 0)
Pin