Freescale Semiconductor DSP56311 Manuals

Manuals and User Guides for Freescale Semiconductor DSP56311. We have 2 Freescale Semiconductor DSP56311 manuals available for free PDF download: User Manual, Technical Data Manual

Freescale Semiconductor DSP56311 User Manual (360 pages)

24-bit digital signal processor (DSP)

Brand: Freescale Semiconductor | Category: Signal Processors | Size: 4.23 MB

DSP56311 Overview
4
Table of Contents
5
DSP56311 Overview

13
- Manual Organization
  13
- Manual Conventions
  14
- Manual Revision History for Revision 2
  16
- DSP56300 Core
  17
- Features
  17
- DSP56300 Core Functional Blocks
  18
  - Data ALU
    18
    
    Data ALU Registers
    19
- Address Generation Unit (AGU)
  19
- Multiplier-Accumulator (MAC)
  19
- Program Control Unit (PCU)
  20
  - PLL and Clock Oscillator
    21
- JTAG TAP and Once Module
  21
  - Internal Memory
    21
- External Memory Expansion
  22
- Internal Buses
  22
- Dma
  24
- Peripherals
  24
  - GPIO Functionality
    24
  - Hi08
    24
  - Essi
    25
  - Sci
    25
  - Timer Module
    26
  - Efcop
    26
Signals/Connections

27
- Power
  29
- Clock
  30
- Ground
  30
- Pll
  30
- External Memory Expansion Port (Port A)
  31
  - External Address Bus
    31
  - External Data Bus
    31
  - External Bus Control
    32
- Interrupt and Mode Control
  34
- Enhanced Synchronous Serial Interface 0
  38
- Enhanced Synchronous Serial Interface 1
  38
- Sci
  43
- Timers
  44
- JTAG and Once Interface
  45
Memory Configuration

47
- Program Memory Space
  47
- Internal Program Memory
  48
- Memory Switch Modes-Program Memory
  48
  - Instruction Cache
    49
  - Program Bootstrap ROM
    49
- Data Memory Space
  49
  - Internal X Data Memory
    50
- Memory Switch Modes-X Data Memory
  50
  - Internal X I/O Space
    51
- Y Data Memory Space
  51
  - Internal y Data Memory
    51
- Memory Switch Modes-Y Data Memory
  52
  - Internal y I/O Space
    53
  - External y I/O Space
    53
- Dynamic Memory Configuration Switching
  53
- Memory Maps
  54
Core Configuration

75
Programming the Peripherals

109
- JTAG Identification (ID) Register
  107
- Mapping the Control Registers
  109
- Peripheral Initialization Steps
  109
- Data Transfer Methods
  110
  - Polling
    111
  - Interrupts
    111
  - Dma
    112
- Reading Status Registers
  110
- Advantages and Disadvantages
  113
- General-Purpose Input/Output (GPIO)
  114
  - Port B Signals and Registers
    114
  - Port C Signals and Registers
    115
  - Port D Signals and Registers
    115
  - Port E Signals and Registers
    115
- Triple Timer Signals and Registers
  116
Host Interface (HI08)

117
- Features
  117
  - DSP Core Interface
    117
  - Host Processor Interface
    117
- Host Port Signals
  119
- Overview
  120
- Operation
  121
  - Software Polling
    122
- Core Interrupts and Host Commands
  122
  - Core DMA Access
    124
  - Host Requests
    124
  - Endian Modes
    125
- Boot-Up Using the HI08 Host Port
  127
- DSP Core Programming Model
  127
- Host Control Register (HCR)
  128
  - Host Status Register (HSR)
    129
- Host Data Direction Register (HDDR)
  130
- Host Base Address Register (HBAR)
  131
- Host Data Register (HDR)
  131
- Host Port Control Register (HPCR)
  132
- DSP-Side Registers after Reset
  136
- Host Receive (HRX) Register
  136
- Host Transmit (HTX) Register
  136
- Host Programmer Model
  137
- Interface Control Register (ICR)
  138
- Command Vector Register (CVR)
  140
- Interface Status Register (ISR)
  141
- Interrupt Vector Register (IVR)
  143
- Receive Data Registers (RXH:RXM:RXL)
  143
- Host-Side Registers after Reset
  144
- Transmit Data Registers (TXH:TXM:TXL)
  144
- Programming Model Quick Reference
  145
Enhanced Synchronous Serial Interface (ESSI)

149
- ESSI Data and Control Signals
  150
- ESSI Enhancements
  150
- Serial Transmit Data Signal (STD)
  150
- Serial Receive Data Signal (SRD)
  151
  - Serial Clock (SCK)
    151
  - Serial Control Signal (SC0)
    151
  - Serial Control Signal (SC1)
    152
  - Serial Control Signal (SC2)
    153
- Operation
  154
  - ESSI after Reset
    154
  - Initialization
    154
  - Exceptions
    155
- Normal/Network/On-Demand Mode Selection
  157
- Operating Modes: Normal, Network, and On-Demand
  157
- Frame Sync Length for Multiple Devices
  158
- Frame Sync Signal Format
  158
- Synchronous/Asynchronous Operating Modes
  158
  - Frame Sync Selection
    158
- Byte Format (LSB/MSB) for the Transmitter
  159
  - Flags
    160
- Word Length Frame Sync and Data Word Timing
  159
  - Frame Sync Polarity
    159
- ESSI Programming Model
  160
- ESSI Control Register a (CRA)
  161
- ESSI Control Register B (CRB)
  165
- ESSI Status Register (SSISR)
  174
- ESSI Receive Data Register (RX)
  176
- ESSI Receive Shift Register
  176
- ESSI Transmit Shift Registers
  176
- ESSI Time Slot Register (TSR)
  179
- ESSI Transmit Data Registers (TX[2-0])
  179
- Transmit Slot Mask Registers (TSMA, TSMB)
  179
- Receive Slot Mask Registers (RSMA, RSMB)
  181
- GPIO Signals and Registers
  182
- Port Control Registers (PCRC and PCRD)
  182
- Port Direction Registers (PRRC and PRRD)
  182
- Port Data Registers (PDRC and PDRD)
  183
Serial Communication Interface (SCI)

185
- Operating Modes
  185
  - Synchronous Mode
    186
  - Asynchronous Mode
    186
  - Multidrop Mode
    186
- I/O Signals
  187
  - Receive Data (RXD)
    188
  - Transmit Data (TXD)
    188
  - SCI Serial Clock (SCLK)
    188
- Transmitting Data and Address Characters
  187
  - Wired-OR Mode
    187
  - Idle Line Wakeup
    187
  - Address Mode Wakeup
    187
- SCI after Reset
  188
- SCI Initialization
  190
- Bootstrap Loading through the SCI (Boot Mode $2 or RA)
  191
- Preamble, Break, and Data Transmission Priority
  191
- Exceptions
  192
- SCI Programming Model
  192
- SCI Control Register (SCR)
  194
  - SCI Status Register (SSR)
    199
- SCI Clock Control Register (SCCR)
  201
  - SCI Data Registers
    203
- SCI Receive Register (SRX)
  204
- SCI Transmit Register (STX)
  205
- GPIO Signals and Registers
  206
- Port E Control Register (PCRE)
  206
- Port E Data Register (PDRE)
  207
Triple Timer Module

209
- Port E Direction Register (PRRE)
  207
- Overview
  209
- Triple Timer Module Block Diagram
  209
- Individual Timer Block Diagram
  210
- Operation
  211
  - Timer after Reset
    211
  - Timer Initialization
    211
  - Timer Exceptions
    212
- Operating Modes
  213
  - Triple Timer Modes
    213
    
    Timer GPIO (Mode 0)
    213
    
    Timer Pulse (Mode 1)
    215
    
    Timer Toggle (Mode 2)
    216
- Timer Event Counter (Mode 3)
  218
- Signal Measurement Modes
  219
- Measurement Input Width (Mode 4)
  220
- Measurement Input Period (Mode 5)
  221
- Measurement Capture (Mode 6)
  223
  - Pulse Width Modulation
    224
  - Watchdog Modes
    226
    
    Watchdog Pulse (Mode 9)
    227
- Watchdog Toggle (Mode 10)
  228
  - Reserved Modes
    228
  - Special Cases
    229
  - DMA Trigger
    229
- Triple Timer Module Programming Model
  229
  - Prescaler Counter
    229
- Timer Prescaler Load Register (TPLR)
  230
- Timer Prescaler Count Register (TPCR)
  231
- Timer Control/Status Register (TCSR)
  232
- Timer Compare Register (TCPR)
  236
- Timer Load Register (TLR)
  236
- Timer Count Register (TCR)
  237
Enhanced Filter Coprocessor

239
- Features
  239
- Architecture Overview
  240
- PMB Interface
  241
- EFCOP Memory Banks
  242
- Filter Multiplier and Accumulator (FMAC)
  243
- EFCOP Initialization
  245
  - FIR Initialization
    245
  - IIR Initialization
    245
- EFCOP Operation
  245
- EFCOP Operation Summary
  245
- FIR Filter Type
  246
  - FIR Operating Modes
    246
    
    Real Mode
    246
    
    Complex Mode
    247
- Alternating Complex Mode
  247
  - Magnitude Mode
    248
- Adaptive Mode Option
  248
- Coefficient Update Option
  248
- FIR Filter Type Processing Options
  248
- IIR Filter Type
  249
- Multichannel Mode Option
  249
  - Decimation Option
    249
- EFCOP Data Transfer Examples
  250
- DMA Input/Dma Output
  252
- EFCOP Operation Examples
  252
  - Real FIR Filter
    252
- DMA Input/Polling Output
  257
- DMA Input/Interrupt Output
  259
- Real FIR Filter with Decimation by M
  262
  - Adaptive FIR Filter
    263
- Implementation Using Polling
  264
- Implementation Using DMA Input and Interrupt Output
  265
- Updating an FIR Filter
  265
- Input Sequence (Input.asm)
  270
- Verification for Filter Examples
  270
- Filter Coefficients (Coefs.asm)
  271
- Output Sequence for Examples 10-1, 10-2, and 10-3
  271
- Desired Signal for Example 10-4
  272
- Output Sequence for Example 10-4
  272
- EFCOP Programming Model
  273
- Filter Data Input Register (FDIR)
  273
- Filter Data Output Register (FDOR)
  273
- Filter Count (FCNT) Register
  274
- Filter K-Constant Input Register (FKIR)
  274
- EFCOP Control Status Register (FCSR)
  275
- EFCOP ALU Control Register (FACR)
  278
- EFCOP Coefficient Base Address (FCBA)
  279
- EFCOP Data Base Address (FDBA)
  279
- Decimation/Channel Count Register (FDCH)
  280
- EFCOP Interrupt Vectors
  281
Bootstrap Program

283
- Bootstrap Code
  283
- Internal I/O Equates
  291
- Interrupt Equates
  302
Programming Reference

306
- Internal I/O Memory Map
  306
- Interrupt Sources and Priorities
  315
- Programming Sheets
  317

Freescale Semiconductor DSP56311 Technical Data Manual (96 pages)

24-Bit Digital Signal Processor

Brand: Freescale Semiconductor | Category: Signal Processors | Size: 1.7 MB

Table of Contents
2
Features
3
Target Applications
4
Product Documentation
4
Chapter 1 Signals/Connections

5
- Power
  7
- Ground
  7
- Clock
  7
- External Memory Expansion Port (Port A)
  8
- Interrupt and Mode Control
  11
- Host Interface (HI08)
  12
  - Host Port Usage Considerations
    12
  - Host Port Configuration
    12
- Enhanced Synchronous Serial Interface 0 (ESSI0)
  15
- Enhanced Synchronous Serial Interface 1 (ESSI1)
  16
- Serial Communication Interface (SCI)
  17
- Timers
  18
- JTAG and Once Interface
  19
Chapter 2 Specifications

21
- Maximum Ratings
  21
- Thermal Characteristics
  22
- DC Electrical Characteristics
  23
- AC Electrical Characteristics
  24
Chapter 3 Packaging

61
- Package Description
  62
- MAP-BGA Package Mechanical Drawing
  70
Chapter 4 Design Considerations

71

Freescale Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More Freescale Semiconductor Manuals

Freescale Semiconductor DSP56311 Manuals

Freescale Semiconductor DSP56311 User Manual (360 pages)

Table of Contents

DSP56311 Overview

Signals/Connections

Memory Configuration

Core Configuration

Programming the Peripherals

Host Interface (HI08)

Enhanced Synchronous Serial Interface (ESSI)

Serial Communication Interface (SCI)

Triple Timer Module

Enhanced Filter Coprocessor

Bootstrap Program

Programming Reference

Freescale Semiconductor DSP56311 Technical Data Manual (96 pages)

Table of Contents

Chapter 1 Signals/Connections

Chapter 2 Specifications

Chapter 3 Packaging

Chapter 4 Design Considerations

Related Products

Freescale Semiconductor Categories