Efcop Data Base Address (Fdba); Efcop Coefficient Base Address (Fcba) - Freescale Semiconductor DSP56311 User Manual

Table 10-8. EFCOP ALU Control Register (FACR) Bits (Continued)
Bit
Bit Name
Number
1–0 FSCL[1–0]

10.4.7 EFCOP Data Base Address (FDBA)

The FDBA is a 16-bit read/write counter register used as an address pointer to the EFCOP FDM
bank. FDBA points to the location to write the next data sample. The FDBA points to a modulo
delay buffer of size M, defined by the filter length (M = FCNT[11:0] + 1). The address range of
this modulo delay buffer is defined by lower and upper address boundaries. The lower address
boundary is the FDBA value with 0 in the k-LSBs, where
k
multiple of 2 . The upper boundary is equal to the lower boundary plus (M – 1). Since
once M has been chosen (that is, FCNT has been assigned), a sequential series of data memory
blocks (each of length 2
filtering can be located. If
k
. The address pointer is not required to start at the lower address boundary or to end on the
2 – M
upper address boundary. It can point anywhere within the defined modulo address range. If the
data address pointer (FDBA) increments and reaches the upper boundary of the modulo buffer, it
will wrap around to the lower boundary.

10.4.8 EFCOP Coefficient Base Address (FCBA)

The FCBA is a 16-bit read/write counter register used as an address pointer to the EFCOP FCM
bank. FCBA points to the first location of the coefficient table. The FCBA points to a modulo
buffer of size M, defined by the filter length (M = FCNT[11:0] + 1). The address range of this
modulo buffer is defined by lower and upper address boundaries. The lower address boundary is
the FCBA value with 0 in the k-LSBs, where
The upper boundary is equal to the lower boundary plus (M – 1). Since
chosen (that is, FCNT has been assigned), a sequential series of coefficient memory blocks (each
k
of length 2 ) is created where multiple circular buffers for multichannel filtering can be located.
<
k
If , there will be a space between sequential circular buffers of
M 2
pointer must be assigned to the lower address boundary (that is, it must have 0 in its k-LSBs). In
a compute session, the coefficient address pointer always starts at the lower boundary and ends at
the upper address boundary. Therefore, a FCBA read always gives the value of the lower address
boundary.
Freescale Semiconductor
Reset
Value
0 Filter Scaling (FSCL)
These read/write control bits select the scaling factor of the FMAC result:
• FSCL = 00—Scaling factor = 1 (no shift)
• FSCL = 01—Scaling factor = 8 (3-bit arithmetic left shift)
• FSCL = 10—Scaling factor = 16 (4-bit arithmetic left shift)
• FSCL = 11—Reserved for future expansion
To ensure proper operation, never change the FSCL bits unless the EFCOP is in the
individual reset state (that is, FEN = 0).
k
) will be created where multiple circular buffers for multichannel
< k
, there will be a space between sequential circular buffers of
M 2
DSP56311 Reference Manual, Rev. 2
Description
k ≥ ≥
2 M 2
k ≥ ≥ k 1 –
; it therefore must be a multiple of 2
2 M 2
EFCOP Programming Model
–
k 1
; it therefore must be a
M 2
≤ k
, once M has been
M 2
k
. The FCBA address
2 – M
≤ k
,
k
.
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