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Enhanced Filter Coprocessor
Multichannel mode to process multiple, equal-length filter channels (up to 64)
simultaneously with minimal core intervention
Optional input scaling for both FIR and IIR filters
Two filter initialization modes
— No initialization
— Data initialization
Sixteen-bit arithmetic mode support
Three rounding options available:
— No rounding
— Convergent rounding
— Two's complement rounding
Arithmetic saturation mode support for bit-exact applications
Sticky saturation status bit indication
Sticky data/coefficient transfer contention status bit
4-word deep input data buffer for maximum performance
EFCOP-shared and core-shared 12 K-word filter data memory bank and 12 K-word filter
coefficient memory bank
Two memory bank base address pointers, one for data memory (shared with X memory)
and one for coefficient memory (shared with Y memory)
I/O data transfers via core or DMA with minimal core intervention
Core-concurrent operation with minimal core intervention
10.2 Architecture Overview
As Figure 10-1 shows, the EFCOP comprises these main functional blocks:
Peripheral module bus (PMB) interface, including:
— Data input buffer
— Constant input buffer
— Output buffer
— Filter counter
Filter data memory (FDM) bank
Filter coefficient memory (FCM) bank
Filter multiplier accumulator (FMAC) machine
Address generator
Control logic
10-2
DSP56311 Reference Manual, Rev. 2
Freescale Semiconductor
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