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Signals/Connections
2.5.3 External Bus Control
Signal
State During Reset,
Type
Name
AA[0–3]
Output
Tri-stated
RAS[0–3]
Output
RD
Output Tri-stated
WR
Output Tri-stated
TA
Input
Ignored Input
2-6
Table 2-8. External Bus Control Signals
Stop, or Wait
Address Attribute—When defined as AA, these signals are used as chip
selects or additional address lines. The default use defines a priority
scheme under which only one AA signal is asserted at a time. Setting the
AA priority disable (APD) bit (Bit 14) of the OMR disables the priority
mechanism and the lines are used together as four external lines decoded
externally into 16 chip select signals.
Row Address Strobe—When defined as RAS, these signals are used as
RAS for DRAM interface. These signals are tri-statable outputs with
programmable polarity.
Note:
Read Enable—When the DSP is the bus master, RD is asserted to read
external memory on the data bus (D[0–23]). Otherwise, RD is tri-stated.
Write Enable—When the DSP is the bus master, WR is asserted to write
external memory on the data bus (D[0–23]). Otherwise, the signals are
tri-stated.
Transfer Acknowledge—If the DSP56311 is the bus master and there is
no external bus activity, or the DSP56311 is not the bus master, the TA
input is ignored. The TA input is a data transfer acknowledge (DTACK)
function that can extend an external bus cycle indefinitely. Any number of
wait states (1, 2. . .infinity) can be added to the wait states inserted by the
bus control register (BCR) by keeping TA deasserted. In typical operation,
TA is deasserted at the start of a bus cycle, asserted to enable completion
of
the bus cycle, and deasserted before the next bus cycle. The current
bus cycle completes one clock period after TA is deasserted. The number
of wait states is determined by the TA input or by the BCR, whichever is
longer. The BCR sets the minimum number of wait states in external bus
cycles.To use the TA functionality, the BCR must be programmed to at
least one wait state. A zero wait state access cannot be extended by TA
deassertion.
At operating frequencies ≤ 100 MHz, TA can operate synchronously (with
respect to CLKOUT) or asynchronously depending on the setting of the
TAS bit in the Operating Mode Register (OMR). If synchronous mode is
selected, the user is responsible for ensuring that TA transitions occur
synchronous to CLKOUT to ensure correct operation. Synchronous
operation is not supported above 100 MHz and the OMR[TAS] bit must be
set to synchronize the TA signal with the internal clock.
DSP56311 User's Manual, Rev. 2
Signal Description
DRAM access is not supported above 100 MHz.
Freescale Semiconductor
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