Overview - Freescale Semiconductor DSP56311 User Manual

Host Interface (HI08)

6.3 Overview

The HI08 is partitioned into two register banks, as Figure 6-1 shows. The host-side register bank
is accessible only to the host, and the DSP-side register bank is accessible only to the DSP core.
For the host, the HI08 appears as eight byte-wide locations mapped in its external address space.
The DSP-side registers appear to the DSP core as six 24-bit registers mapped into internal I/O X
memory space and therefore accessible via standard DSP56300 instructions and addressing
modes.
Control Registers
HCR = Host Control Register
HSR = Host Status Register
HPCR = Host Port Control Register
HBAR = Host Base Address Register
24 24
HCR HSR
ISR ICR
8 8
Control Registers
ISR = Interface Status Register
ICR = Interface Control Register
CVR = Command Vector Register
IVR = Interrupt Vector Register
6-4
DSP-Side Registers
Core DMA Data Bus
DSP Peripheral Data Bus
24 24 24
HDDR HDR HBAR
Address
Comparator
3
CVR IVR Latch
8 8 8
HOST Bus
Host-Side Registers
Figure 6-1. HI08 Block Diagram
DSP56311 User's Manual, Rev. 2
Data Registers
HTX = Host Transmit Register
HRX = Host Receive Register
HDDR = Host Data Direction Register
HDR = Host Data Register
24 24
HPCR HTX
5
RXH RXM RXL
3 8 8 8
Data Registers
RXH = Receive Register High
RXM = Receive Register Middle
RXL = Receive Register Low
TXH = Transmit Register High
TXM = Transmit Register Middle
TXL = Transmit Register Low
24 24 24
HRX
24 24
TXH TXM TXL
8 8 8
Freescale Semiconductor
DSP
Side
Host
Side