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DSP56311 Overview
inputs. The only difference between them is that the carry propagates in opposite directions. Test
logic determines which of the three summed results of the full adders is output.
Each address ALU can update one address register from its own address register file during one
instruction cycle. The contents of the associated modifier register specify the type of arithmetic
used in the address register update calculation. The modifier value is decoded in the address
ALU.
1.6.3 Program Control Unit (PCU)
The PCU fetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
Program decode controller. Decodes the 24-bit instruction loaded into the instruction
latch and generates all signals for pipeline control.
Program address generator. Contains all the hardware needed for program address
generation, system stack, and loop control.
Program interrupt controller. Arbitrates among all interrupt requests (internal interrupts,
as well as the five external requests
appropriate interrupt vector address.
PCU features include the following:
Position-independent code support
Addressing modes optimized for DSP applications (including immediate offsets)
Instruction cache controller
Internal memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
Hardware system stack
The PCU uses the following registers:
Program counter register
Status register
Loop address register
Loop counter register
Vector base address register
Size register
Stack pointer
Operating mode register
1-8
,
,
IRQA
IRQB
IRQC
DSP56311 User's Manual, Rev. 2
,
, and
), and generates the
IRQD
NMI
Freescale Semiconductor
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