Timer Pulse (Mode 1) - Freescale Semiconductor DSP56311 User Manual

9.3.1.2 Timer Pulse (Mode 1)

Bit Settings
TC3 TC2 TC1
0 0 0
In Mode 1, the timer generates an external pulse on its TIO signal when the timer count reaches a
pre-set value. The TIO signal is loaded with the value of the TCSR[INV] bit. When the counter
matches the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The polarity of the TIO signal is inverted for one timer clock period. If
TCSR[TRM] is set, the counter is loaded with the TLR value on the next timer clock and the
count is resumed. If TCSR[TRM] is cleared, the counter continues to increment on each timer
clock. This process repeats until TCSR[TE] is cleared (disabling the timer).
The TLR value in the TCPR sets the delay between starting the timer and generating the output
pulse. To generate successive output pulses with a delay of X clock cycles between signals, set
the TLR value to X/2 and set the TCSR[TRM] bit. This process repeats until the timer is
disabled.
Mode 1 (internal clock): TRM = 1
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
Freescale Semiconductor
TC0 Mode
1 1 Timer Pulse
first event
N
0 N
M
Figure 9-5. Pulse Mode (TRM = 1)
DSP56311 User's Manual, Rev. 2
Mode Characteristics
Name Function
Timer
N + 1 M
Operating Modes
TIO Clock
Output Internal
N N + 1
pulse width =
timer clock
period
9-7