Watchdog Pulse (Mode 9) - Freescale Semiconductor DSP56311 User Manual

9.3.4.1 Watchdog Pulse (Mode 9)

Bit Settings
TC3 TC2 TC1
1 0 0
In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal to the
period of one timer clock. After the counter reaches the value in the TCPR, if the TCSR[TRM]
bit is set, the counter is loaded with the TLR value on the next timer clock and the count resumes.
Therefore TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared, the
counter continues to increment on each subsequent timer clock. This process repeats until the
timer is disabled (that is, TCSR[TE] is cleared). If the counter overflows, a pulse is output on the
signal with a pulse width equal to the timer clock period. If the INV bit is set, the pulse
TIO
polarity is high (logical 1). If INV is cleared, the pulse polarity is low (logical 0). The counter
reloads when the TLR is written with a new value while the TCSR[TE] bit is set. In Mode 9,
internal logic preserves the
the hardware
RESET
generated when the
TIO
Mode 9 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
Freescale Semiconductor
TC0 Mode
1 9
value and direction for an additional 2.5 internal clock cycles after
TIO
signal is asserted. This convention ensures that a valid
signal resets the DSP56311.
first event
N
0
N
M
float
low
float
high
Figure 9-18. Watchdog Pulse Mode
DSP56311 User's Manual, Rev. 2
Mode Characteristics
Name Function
Pulse Watchdog
(Software does not reset watchdog timer; watchdog times out)
TRM = 1 is not useful for watchdog function
M
N + 1
Operating Modes
TIO
Output
signal is
RESET
M + 1 0
1
pulse width
= timer
clock period
Clock
Internal
9-19