Reading Status Registers; Data Transfer Methods - Freescale Semiconductor DSP56311 User Manual

Programming the Peripherals
contents of the internal X I/O memory space are listed in Appendix B, Programming Reference,
Table B-2.
$FFFFFF
$FFFF80
$FFF000
$FF0000
$000800
$000000
Figure 5-1. Memory Mapping of Peripherals Control Registers

5.3 Reading Status Registers

Each peripheral has a read-only status register that indicate the state of the peripheral at a given
time. The HI08, ESSI, and SCI have dedicated status registers. The triple timer has status bits
embedded within a control/status register. Changes in the status bits can generate interrupt
conditions. For example, the HI08 has a host status register with two host flag bits that can be
encoded by the host to generate an interrupt in the DSP.

5.4 Data Transfer Methods

Peripheral I/O on the DSP56311 can be accomplished in three ways:
Polling
Interrupts
DMA
5-2
X-Data Memory
Internal I/O
External
Internal
Reserved
External
Internal
X-Data RAM
2 K (default)
DSP56311 User's Manual, Rev. 2
Peripherals Control Registers
Memory Space
Freescale Semiconductor