Pll Control Register (Pctl) - Freescale Semiconductor DSP56311 User Manual

Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority
Lowest

4.5 PLL Control Register (PCTL)

The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by configuring
the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write register that directs
the on-chip PLL operation. (See Figure 4-5.)
23 22 21
PD3 PD2 PD1
11 10 9
MF11 MF10 MF9
Table 4-7 defines the DSP56311 PCTL bits. Changing the following bits may cause the PLL to
lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.
Table 4-7. PLL Control Register (PCTL) Bit Definitions
Bit Number Bit Name
23–20 PD[3–0]
19 COD
Freescale Semiconductor
SCI receive data
SCI transmit data
SCI idle line
SCI timer
TIMER0 overflow interrupt
TIMER0 compare interrupt
TIMER1 overflow interrupt
TIMER1 compare interrupt
TIMER2 overflow interrupt
TIMER2 compare interrupt
EFCOP Data Input Buffer Empty
EFCOP Data Output Buffer Full
20 19 18
PD0 COD PEN
8 7 6
MF8 MF7 MF6
Figure 4-5. PLL Control Register (PCTL)
Reset Value
0 Predivider Factor
Define the predivision factor (PDF) to be applied to the PLL input frequency.
The PD[3–0] bits are cleared during DSP56311 hardware reset, which
corresponds to a PDF of one.
0 Clock Output Disable
Controls the output buffer of the clock at the CLKOUT pin. When COD is set,
the CLKOUT output is pulled high. When COD is cleared, the CLKOUT pin
provides a 50 percent duty cycle clock.
DSP56311 User's Manual, Rev. 2
Interrupt Source
17 16 15
PSTP XTLD XTLR
5 4 3
MF5 MF4 MF3
Description
PLL Control Register (PCTL)
14 13 12
DF2 DF1 DF0
2 1 0
MF2 MF1 MF0
4-19