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Enhanced Filter Coprocessor
10.4.9 Decimation/Channel Count Register (FDCH)
The FDCH is a read/write register that sets the number of channels used in multichannel mode
(FCHL) and sets the decimation ratio in FIR filter mode. FDCH must be written before the FEN
enables the EFCOP. FDCH should be changed only when the EFCOP is in individual reset state
(FEN = 0); otherwise, improper operation may result. The number stored in FCHL is used by the
EFCOP address generation logic to generate the correct address for the FDM bank and for the
FCM bank in multichannel mode. When the EFCOP enable bit (FEN) is cleared, the EFCOP is in
individual reset state. In this state, the EFCOP is inactive, and the contents of FDCH register are
preserved.
23
22
21
11
10
9
FDCM3
FDCM2
FDCM1
Reserved bit; read as 0; write with 0 for future compatibility
=
Table 10-9. Decimation/Channel Count Register (FDCH) Bits
Bit
Bit Name
Number
23–12
11–8
FDCM[3–0]
7–6
5–0
FCHL[5–0]
10-42
20
19
18
8
7
6
FDCM0
Reset
Value
0
These bits are reserved and unused. They read as 0; write with 0 for future
compatibility.
0
Filter Decimation
These read/write control bits select the decimation function. There are 16 decimation
factor options (from 1 to 16). To ensure proper operation, never change the FDCM bits
unless the EFCOP is in the individual reset state (FEN = 0).
0
Reserved and unused. They read as 0; write with 0 for future compatibility.
0
Filter Channels
These read/write control bits determine the number of filter channels to process
simultaneously (from 1 to 64) in multichannel mode. The number represented by the
FCHL bits is one less than the number of channels to be processed; that is, if FCHL =
0, then 1 channel is processed; if FCHL =1, then 2 channels are processed; and so on.
To ensure proper operation, never change the FCHL bits unless the EFCOP is in the
individual reset state (FEN = 0).
DSP56311 Reference Manual, Rev. 2
17
16
15
5
4
3
FCHL5
FCHL4
FCHL3
Description
14
13
12
2
1
0
FCHL2
FCHL1
FCHL0
Freescale Semiconductor
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