Sci Receive Register (Srx) - Freescale Semiconductor DSP56311 User Manual

Serial Communication Interface (SCI)
23 16
SRX
RXD
Note: SRX is the same register decoded at three different addresses.
23 16
STX
SCI Transmit Data Shift Register
23 16
Note: Bytes are masked on the fly.
STX is the same register decoded at four different addresses.
Figure 8-7. SCI Programming Model—Data Registers

8.6.4.1 SCI Receive Register (SRX)

Data bits received on the
complete word is received, the data portion of the word is transferred to the byte-wide SRX. This
process converts serial data to parallel data and provides double buffering. Double buffering
promotes flexibility and increased throughput since the programmer can save (and process) the
previous word while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the
contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the
data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed into the
middle byte of the bus, and when SRXH is read, the contents of SRX are placed into the high
byte with the remaining bits are read as 0s. This way of mapping SRX efficiently packs three
bytes into one 24-bit word by ORing three data bytes read from the three addresses.
The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial word.
The SCR receive clock mode (RCM) defines the clock source.
8-20
15 8 7
SRX
SRX
SCI Receive Data Shift Register
(a) Receive Data Register
15 8 7
STX
STX
15 8 7
STXA
(b) Transmit Data Register
signal are shifted into the SCI receive shift register. When a
RXD
DSP56311 User's Manual, Rev. 2
0
SCI Receive Data Register High (Read Only)
SCI Receive Data Register Middle (Read Only)
SCI Receive Data Register Low (Read Only)
0
SCI Transmit Data Register High (Write Only)
SCI Transmit Data Register Middle (Write Only)
SCI Transmit Data Register Low (Write Only)
TXD
0
SCI Transmit Data Address Register (Write Only)
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