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Mode 4 (internal clock): TRM = 1
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
TCR
TIO pin
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
Figure 9-12. Pulse Width Measurement Mode, TRM = 0
9.3.2.2 Measurement Input Period (Mode 5)
Bit Settings
TC3
TC2
TC1
0
1
0
In Mode 5, the timer counts the period between the reception of signal edges of the same polarity
across the
signal. The value of the INV bit determines whether the period is measured
TIO
between consecutive low-to-high (0 to 1) transitions of
(1 to 0) transitions of
cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on
the
input signal, the counter is loaded with the TLR value. On the next signal transition of the
TIO
same polarity that occurs on
TCSR[TCIE] bit is set. The contents of the counter load into the TCR. The TCR then contains the
value of the time that elapsed between the two signal transitions on the
second signal transition, if the TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter
and enable the timer. The counter is repeatedly loaded and incremented until the timer is
disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it overflows.
Freescale Semiconductor
first event
N
0
N
width being measured
TC0
Mode
1
5
. If INV is set, high-to-low signal transitions are selected. If INV is
TIO
, TCSR[TCF] is set, and a compare interrupt is generated if the
TIO
DSP56311 User's Manual, Rev. 2
N + 1
M
Mode Characteristics
Name
Function
Input period
Measurement
or between consecutive high-to-low
TIO
Operating Modes
M
Next 0-to-1 edge
N + 1
on TIO starts
counter from current
count and process
repeats. Overflow
may occur (TOF = 1).
Interrupt Service
reads TCR for
accumulated width
of M - N clock periods.
TIO
Clock
Input
Internal
signal. After the
TIO
9-13
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