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2.12 JTAG and OnCE Interface
The DSP56300 family and in particular the DSP56311 support circuit-board test strategies that
are based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the
industry standard developed under the sponsorship of the Test Technology Committee of IEEE
and the JTAG.
The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its
peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the
OnCE module are provided through the JTAG TAP signals.
For programming models, see the chapter on debugging support in the DSP56300 Family
Manual.
Signal
Type
Name
TCK
Input
TDI
Input
TDO
Output
TMS
Input
TRST
Input
DE
Input/
Output
Freescale Semiconductor
Table 2-15. OnCE/JTAG Interface
State
During
Reset
Input
Test Clock—A test clock input signal to synchronize the JTAG test logic.
Input
Test Data Input—A test data serial input signal used for test instructions and
data. TDI is sampled on the rising edge of TCK and has an internal pull-up
resistor.
Tri-stated
Test Data Output—A test data serial output signal for test instructions and
data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR
controller states. TDO changes on the falling edge of TCK.
Input
Test Mode Select—Sequences the test controller's state machine. TMS is
sampled on the rising edge of TCK and has an internal pull-up resistor.
Input
Test Reset—Initializes the test controller asynchronously. TRST has an
internal pull-up resistor. TRST must be asserted after power up.
Input
Debug Event—As an input, provides a means of entering debug mode from an
external command controller. As an output, provides a means of
acknowledging that the chip has entered debug mode. Asserted as an input,
DE causes the DSP56300 core to finish executing the current instruction, save
the instruction pipeline information, enter debug mode, and wait for commands
from the debug serial input line. This signal is asserted as an output for three
clock cycles when the chip enters debug mode as a result of a debug request
or a breakpoint condition. The DE has an internal pull-up resistor.
DE is not a standard part of the JTAG TAP controller. The signal connects
directly to the OnCE module to initiate debug mode directly or to provide a
direct external indication that the chip has entered debug mode. All other
interaction with the OnCE module must occur through the JTAG port.
DSP56311 User's Manual, Rev. 2
JTAG and OnCE Interface
Signal Description
2-19
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