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Signals/Connections
The DSP56311 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1
diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Power (V
)
CC
Ground (GND)
Clock
PLL
Address bus
Data bus
Bus control
Interrupt and mode control
Host interface (HI08)
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
OnCE/JTAG Port
Notes:
1.
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
2.
Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
5.
There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see
Chapter 3).
Note:
The Clock Output (
are supported by the DSP56311 at operating frequencies up to 100 MHz. Therefore, above 100 MHz, you must
enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register.
When set, the ABE bit eliminates the required set-up and hold times for
addition, DRAM access is not supported above 100 MHz.
Freescale Semiconductor
Table 1-1.
DSP56311 Functional Signal Groupings
Functional Group
),
,
,
CLKOUT
BCLK
BCLK
CAS
DSP56311 Technical Data, Rev. 8
, and
signals used by other DSP56300 family members
RAS[0–3]
and
BB
Number of
Signals
20
66
2
3
18
1
Port A
24
13
5
2
Port B
16
3
Ports C and D
12
4
Port E
3
3
6
with respect to
BG
CLKOUT
1
. In
1-1
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