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Signals/Connections
The DSP56311 input and output signals are organized into functional groups as shown in Table
2-1. Figure 2-1 diagrams the DSP56311 signals by functional group. The remainder of this
chapter describes the signal pins in each functional group.
Power (V
)
CC
Ground (GND)
Clock
PLL
Address bus
Data bus
Bus control
Interrupt and mode control
Host interface (HI08)
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
OnCE/JTAG Port
Note:
1.
Port A signals define the external memory interface port, including the external address bus, data bus, and
control signals.
2.
Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
Note:
The DSP56311 supports Clock Output (
DSP56300 family members at operating frequencies up to 100 MHz. Therefore, above
100 MHz, the user must enable bus arbitration by setting the Asynchronous Bus
Arbitration Enable Bit (ABE) in the operating mode register. When set, the ABE bit
eliminates the required setup and hold times for
Freescale Semiconductor
Table 2-1. DSP56311 Functional Signal Groupings
Functional Group
DSP56311 User's Manual, Rev. 2
1
Port A
2
Port B
Ports C and D
4
Port E
),
, and
CLKOUT
BCLK
BCLK
and
with respect to
BB
BG
2
Number of Signals
20
66
2
3
18
24
13
5
16
3
12
3
3
6
signals used by other
.
CLKOUT
2-1
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