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Freescale Semiconductor DSP56311 User Manual

24-bit digital signal processor (dsp)
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DSP56311 U
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M
SER
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ANUAL
DSP56311UM
Rev. 2, December 2005

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Summary of Contents for Freescale Semiconductor DSP56311

  • Page 1 DSP56311 U ’ ANUAL DSP56311UM Rev. 2, December 2005...
  • Page 2 E-mail: support@freescale.com Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee USA/Europe or Locations not listed: regarding the suitability of its products for any particular purpose, nor does Freescale...
  • Page 3 DSP56311 Overview Signals/Connections Memory Configuration Core Configuration Programming the Peripherals Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Triple Timer Module Enhanced Filter Coprocessor Bootstrap Program Programming Reference Index...

  • Page 4: Dsp56311 Overview

    DSP56311 Overview Signals/Connections Memory Configuration Core Configuration Programming the Peripherals Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Triple Timer Module Enhanced Filter Coprocessor Bootstrap Program Programming Reference Index...

  • Page 5: Table Of Contents

    Timers ..............2-18 DSP56311 User’s Manual, Rev. 2...
  • Page 6 Interrupts ..............5-3 DSP56311 User’s Manual, Rev. 2...
  • Page 7 Serial Control Signal (SC0) ........... . 7-3 DSP56311 User’s Manual, Rev. 2...
  • Page 8 Exceptions..............8-8 DSP56311 User’s Manual, Rev. 2...
  • Page 9 Architecture Overview ............10-2 DSP56311 User’s Manual, Rev. 2...
  • Page 10 EFCOP Interrupt Vectors ........... 10-43 DSP56311 User’s Manual, Rev. 2...
  • Page 11 Programming Sheets ............B-12 DSP56311 User’s Manual, Rev. 2...
  • Page 12 Contents DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 13: Dsp56311 Overview

    DSP56311 Overview This manual describes the DSP56311 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56311 is an implementation of the DSP56300 core with a unique configuration of internal memory, cache, and peripherals. Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM), which describes the CPU, core programming models, and instruction set.

  • Page 14: Manual Conventions

    Appendix A, Bootstrap Code. Bootstrap code and equates for the DSP56311. Appendix B, Programming Reference. Peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56311; programming sheets listing the contents of the major DSP56311 registers for programmer’s reference. 1.2 Manual Conventions...
  • Page 15 The word “reset” is used in four different contexts in this manual: — the reset signal, written as RESET — the reset instruction, written as RESET — the reset operating state, written as Reset — the reset function, written as reset DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 16: Manual Revision History For Revision 2

    • Figure B-6, Bus Control Register (BCR) Page B-18 Page B-18 • Figure B-8, Address Attribute Registers (AAR[3–0]) Page B-20 Page B-20 • Figure B-22, Timer Load, Compare, and Count Registers (TLR, TCPR, and TCR) Page B-34 Page B-34 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 17: Features

    In particular, the DSP56311 includes a JTAG port integrated with the Freescale OnCE module. The DSP56311. with its large internal memory arrary of 128 K words and its EFCOP, is well suited for high-end multichannel telecommunication applications, such as multi-line voice/data/fax processing, video conferencing, and general digital signal processing 1.5 DSP56300 Core...

  • Page 18: Dsp56300 Core Functional Blocks

    PLL and clock oscillator JTAG TAP and OnCE module Memory In addition, the DSP56311 provides a set of internal peripherals, discussed in Section 1.9, Peripherals, on page 1-12. 1.6.1 Data ALU The data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.

  • Page 19: Data Alu Registers

    (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in parallel and share common DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 20: Program Control Unit (Pcu)

    Fast auto-return interrupts Hardware system stack The PCU uses the following registers: Program counter register Status register Loop address register Loop counter register Vector base address register Size register Stack pointer Operating mode register DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 21: Pll And Clock Oscillator

    ALUs and to feed two operands simultaneously to the data ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. There is an on-chip 192 x 24-bit bootstrap ROM. For details on internal memory, see Chapter 3, DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 22: External Memory Expansion

    Simultaneous glueless interface to static random access memory (SRAM) and dynamic random access memory (DRAM) 1.7 Internal Buses To provide data exchange between the blocks, the DSP56311 implements the following buses: Peripheral I/O expansion bus to peripherals Program memory expansion bus to program ROM...
  • Page 23 Two 56-bit Accumulators 56-bit Barrel Shifter EXTAL MODA/IRQA XTAL MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1-1. DSP56311 Block Diagram Note: See Section 1.6.6, Internal Memory, on page 1-9 for memory size details. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 1-11...

  • Page 24: Dma

    One-, two-, and three-dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals 1.9 Peripherals In addition to the core features, the DSP56311 provides the following peripherals: As many as 34 user-configurable GPIO signals HI08 to external hosts Dual ESSI...

  • Page 25: Essi

    (up to 12.5 Mbps for a 100 MHz clock). SCI asynchronous protocols include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. This mode allows the DSP56311 to share a single serial line efficiently with other peripherals.

  • Page 26: Timer Module

    24-bit or 16-bit precision arithmetic with full support for saturation arithmetic. A cost-effective and power-efficient coprocessor, the EFCOP accelerates filtering tasks, such as echo cancellation or correlation, concurrently with software running on the DSP core. DSP56311 User’s Manual, Rev. 2 1-14 Freescale Semiconductor...

  • Page 27: Signals/Connections

    Signals/Connections The DSP56311 input and output signals are organized into functional groups as shown in Table 2-1. Figure 2-1 diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 2-1. DSP56311 Functional Signal Groupings...
  • Page 28 D GPIO signals (PD[0–5]), and SCI with Port E GPIO signals (PE[0–2]). TIO[0–2] can be configured as GPIO signals. These signals are not supported above 100 MHz. Figure 2-1. Signals Identified by Functional Group DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 29: Power

    ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs, except V . The user must provide CCQL adequate external decoupling capacitors. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 30: Ground

    Asynchronous Bus Arbitration Enable (ABE) bit in the Operating Mode Register (OMR). When set, the DSP enters the Asynchronous Arbitration mode, which eliminates the BB and BG setup and hold time requirements with respect to CLKOUT. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 31: External Memory Expansion Port (Port A)

    CLKOUT. 2.5 External Memory Expansion Port (Port A) Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS. 2.5.1 External Address Bus Table 2-6.

  • Page 32: External Bus Control

    Ignored Input Transfer Acknowledge—If the DSP56311 is the bus master and there is no external bus activity, or the DSP56311 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2.
  • Page 33 Bus “parking” allows BR to be deasserted even though the depends on BCR[BRH] DSP56311 is the bus master. (See the description of bus “parking” in the BB bit setting: signal description.) The Bus Request Hold (BRH) bit in the BCR allows BR •...

  • Page 34: Interrupt And Mode Control

    External Interrupt Request B—After reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQB is asserted, the processor exits the WAIT state. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 35 0–7 of the Address/Data bus. PB[0–7] Input or Port B 0–7—When the HI08 is configured as GPIO through the HPCR, these Output signals are individually programmed through the HI08 Data Direction Register (HDDR). DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 36 (HRD) after reset. Port B 11—When the HI08 is configured as GPIO through the HPCR, this PB11 Input or signal is individually programmed through the HDDR. Output DSP56311 User’s Manual, Rev. 2 2-10 Freescale Semiconductor...
  • Page 37 PB14 Input or Port B 14—When the HI08 is configured as GPIO through the HPCR, this Output signal is individually programmed through the HDDR. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 2-11...

  • Page 38: Enhanced Synchronous Serial Interface 0

    The default configuration following reset is GPIO. For PC0, signal direction is controlled through the Port C Direction Register (PRRC). This signal is configured as SC00 or PC0 through the Port C Control Register (PCRC). This input is 5 V tolerant. DSP56311 User’s Manual, Rev. 2 2-12 Freescale Semiconductor...
  • Page 39 Port C 5 The default configuration following reset is GPIO. For PC5, signal direction is controlled through PRRC. This signal is configured as STD0 or PC5 through PCRC. This input is 5 V tolerant. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 2-13...
  • Page 40 If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. The Wait processing state does not affect the signal state. DSP56311 User’s Manual, Rev. 2 2-14 Freescale Semiconductor...
  • Page 41 Input or Output The default configuration following reset is GPIO. For PD2, signal direction is controlled through PRRD. This signal is configured as SC12 or PD2 through PCRD. This input is 5 V tolerant. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 2-15...
  • Page 42 If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. The Wait processing state does not affect the signal state. DSP56311 User’s Manual, Rev. 2 2-16 Freescale Semiconductor...

  • Page 43: Sci

    If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. The Wait processing state does not affect the signal state. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 2-17...

  • Page 44: Timers

    Three identical and independent timers are implemented in the DSP56311. Each timer can use internal or external clocking and can either interrupt the DSP56311 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events.

  • Page 45: Jtag And Once Interface

    JTAG and OnCE Interface 2.12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56311 support circuit-board test strategies that are based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG.
  • Page 46 Signals/Connections DSP56311 User’s Manual, Rev. 2 2-20 Freescale Semiconductor...

  • Page 47: Memory Configuration

    Memory Configuration Like all members of the DSP56300 core family, the DSP56311 addresses three sets of 16 M × 24-bit memory internally: program, X data, and Y data. Each of these memory spaces includes both internal and external memory (accessed through the external memory interface).

  • Page 48: Internal Program Memory

    1K program words (locations $0 – $3FF). The lowest external program memory location in this mode is $18000, while program memory locations $10000 – $17FFF are considered reserved and should not be accessed. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 49: Instruction Cache

    Mode, on page 3-10.) 3.1.4 Program Bootstrap ROM The program memory space occupying locations $FF0000–$FF00BF includes the internal bootstrap ROM. This ROM contains the 192-word DSP56311 bootstrap program. 3.2 X Data Memory Space The X data memory space consists of the following:...

  • Page 50: Internal X Data Memory

    X memory are switched to internal program memory, and therefore the highest internal X memory location is $9FFF. The X memory space at the switched locations ($A000 – $BFFF) becomes reserved and should not be accessed. The lowest external X memory location is $C000. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 51: Internal X I/O Space

    3.2.3 Internal X I/O Space One part of the on-chip peripheral registers and some of the DSP56311 core registers occupy the top 128 locations of the X data memory ($FFFF80 – $FFFFFF). This area is referred to as the...

  • Page 52: Memory Switch Modes-Y Data Memory

    EFCOP to the same memory bank (of 256 locations) of the shared memory are not permitted. It is your responsibility to prevent such simultaneous accesses. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 53: Internal Y I/O Space

    OMR bits. CAUTION To ensure that dynamic switching is trouble-free, do not allow any accesses (including instruction fetches) to or from the affected address ranges in program and data memories during the switch cycle. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 54: Sixteen-Bit Compatibility Mode Configuration

    (after the switch) and thus may execute improperly. 3.5 Sixteen-Bit Compatibility Mode Configuration The sixteen-bit compatibility (SC) mode allows the DSP56311 to use DSP56000 object code without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode to this special 16-bit mode.
  • Page 55 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-1. Memory Switch Off, Cache Off, 24-Bit Mode (Default) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 56 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-2. Memory Switch Off, Cache On, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 3-10 Freescale Semiconductor...
  • Page 57 • Lowest 10K of X data RAM and 410K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-3. Memory Switch On (MSW = 00), Cache Off, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-11...
  • Page 58 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-4. Memory Switch On (MSW = 00), Cache On, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 3-12 Freescale Semiconductor...
  • Page 59 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-5. Memory Switch On (MSW = 01), Cache Off, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-13...
  • Page 60 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-6. Memory Switch On (MSW = 01), Cache On, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 3-14 Freescale Semiconductor...
  • Page 61 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-7. Memory Switch On (MSW = 10), Cache Off, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-15...
  • Page 62 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-8. Memory Switch On (MSW = 10), Cache On, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 3-16 Freescale Semiconductor...
  • Page 63 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-9. Memory Switch On (MSW = 11), Cache Off, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-17...
  • Page 64 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-10. Memory Switch On (MSW = 11), Cache On, 24-Bit Mode DSP56311 User’s Manual, Rev. 2 3-18 Freescale Semiconductor...
  • Page 65 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-11. Memory Switch Off, Cache Off, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-19...
  • Page 66 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-12. Memory Switch Off, Cache On, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 3-20 Freescale Semiconductor...
  • Page 67 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-13. Memory Switch On (MSW = 00), Cache Off, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-21...
  • Page 68 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-14. Memory Switch On (MSW = 00), Cache On, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 3-22 Freescale Semiconductor...
  • Page 69 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-15. Memory Switch On (MSW = 01), Cache Off, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-23...
  • Page 70 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-16. Memory Switch On (MSW = 01), Cache On, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 3-24 Freescale Semiconductor...
  • Page 71 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-17. Memory Switch On (MSW = 10), Cache Off, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-25...
  • Page 72 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-18. Memory Switch On (MSW = 10), Cache On, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 3-26 Freescale Semiconductor...
  • Page 73 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-19. Memory Switch On (MSW = 11), Cache Off, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 3-27...
  • Page 74 • Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller. Figure 3-20. Memory Switch On (MSW = 11), Cache On, 16-Bit Mode DSP56311 User’s Manual, Rev. 2 3-28 Freescale Semiconductor...

  • Page 75: Core Configuration

    Family Manual. 4.1 Operating Modes The DSP56311 begins operation by leaving the Reset state and going into one of eight operating modes. As the DSP56311 exits the Reset state, it loads the values of MODA, MODB, MODC, and MODD into bits MA, MB, MC, and MD of the OMR. These bit settings determine the chip’s operating mode, which in turn determines the bootstrap program option the chip uses to start up.
  • Page 76 Core Configuration OMR[MA–MD] bits), and the reset vector address to which the DSP56311 jumps once it leaves the Reset state. Table 4-1. DSP56311 Operating Modes Reset Mode MODD MODC MODB MODA Description Vector $C00000 Expanded mode Bypasses the bootstrap ROM, and the DSP56311 starts fetching instructions beginning at address $C00000.
  • Page 77 Operating Modes Table 4-1. DSP56311 Operating Modes (Continued) Reset Mode MODD MODC MODB MODA Description Vector $FF0000 Bootstrap through SCI Instructions are loaded through the SCI. The bootstrap program sets the SCI to operate in 10-bit asynchronous mode, with 1 start bit, 8 data bits, 1 stop bit, and no parity.

  • Page 78: Bootstrap Program

    RAM segment from an external byte-wide EPROM, the SCI, or the host port. The bootstrap program code is listed in Appendix A. Upon exiting the Reset state, the DSP56311 samples the MOD[A–D] signal lines and loads their values into OMR[MA–MD]. The mode input signals (MOD[A–D]) and the resulting MA, MB, MC, and MD bits determine which bootstrap mode the DSP56311 enters (see Table 4-1).
  • Page 79 15 14 13 12 11 10 CP[1–0] RM SM CE SA FV LF DM SC S[1–0] I[1–0] Reset: Reserved bit. Read as zero; write to zero for future compatibility Figure 4-1. Status Register (SR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 80 In this mode, 16-bit data is right-aligned in the 24-bit memory locations, registers, and 24-bit register portions. Shifting, limiting, rounding, arithmetic instructions, and moves are performed accordingly. For details on Sixteen-Bit Arithmetic mode, consult the DSP56300 Family Manual . DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 81 Therefore, do not change Y0 when running the double-precision multiply algorithm. If the Data ALU must be used in an interrupt service routine, Y0 should be saved with other Data ALU registers to be used and restored before the interrupt routine terminates. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 82 OR S (previous) Scale down S = (A47 XOR A46) OR (B47 XOR B46) OR S (previous) Scale up S = (A45 XOR A44) OR (B45 XOR B44) OR S (previous) Reserved — S undefined DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 83 Scaling Mode Integer Portion No scaling U = (Bit 47 XOR Bit 46) Scale down U = (Bit 48 XOR Bit 47) Scale up U = (Bit 46 XOR Bit 45) Reserved U undefined DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 84: Operating Mode Register (Omr)

    RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode bits (MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC, MODB, and MODA respectively. Table 4-3 defines the DSP56311 OMR bits. DSP56311 User’s Manual, Rev. 2...
  • Page 85 Address Trace Enable (ATE) bit enables Address Trace mode. The Address Trace mode is a debugging tool that reflects internal memory accesses on the external address bus. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-11...
  • Page 86 If the bit is set, Burst mode is enabled, and up to four program words are fetched from the external memory when an instruction cache miss is detected. DSP56311 User’s Manual, Rev. 2 4-12 Freescale Semiconductor...
  • Page 87 MODB, and MODA, respectively. After the DSP56300 core leaves the Reset state, MD–MA can be changed under program control. * The MD–MA bits reflect the corresponding value of the mode input (that is, MODD–MODA), respectively. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-13...

  • Page 88: Configuring Interrupts

    4.4.1 Interrupt Priority Registers (IPRC and IPRP) There are two interrupt priority registers in the DSP56311. The IPRC (Figure 4-3) is dedicated to DSP56300 core interrupt sources, and IPRP (Figure 4-3) is dedicated to DSP56311 peripheral interrupt sources. D5L1...

  • Page 89: Interrupt Table Memory Map

    DSP56311 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions. In the DSP56311, only some of the 128 vector addresses are used for specific interrupt sources. The remaining interrupt vectors are reserved and can be used for DSP56311 User’s Manual, Rev.
  • Page 90 ESSI0 receive data with exception status VBA:$34 0–2 ESSI0 receive last slot VBA:$36 0–2 ESSI0 transmit data VBA:$38 0–2 ESSI0 transmit data with exception status VBA:$3A 0–2 ESSI0 transmit last slot VBA:$3C 0–2 Reserved VBA:$3E 0–2 Reserved DSP56311 User’s Manual, Rev. 2 4-16 Freescale Semiconductor...

  • Page 91: Processing Interrupt Source Priorities Within An Ipl

    IPL is serviced first. When several interrupt requests with the same IPL are pending, another fixed-priority structure within that IPL determines which interrupt source is serviced first. Table 4-6 shows this fixed-priority list of interrupt sources within an IPL, from DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-17...
  • Page 92 ESSI1 RX data with exception interrupt ESSI1 RX data interrupt ESSI1 receive last slot interrupt ESSI1 TX data with exception interrupt ESSI1 transmit last slot interrupt ESSI1 TX data interrupt SCI receive data with exception interrupt DSP56311 User’s Manual, Rev. 2 4-18 Freescale Semiconductor...

  • Page 93: Pll Control Register (Pctl)

    MF10 Figure 4-5. PLL Control Register (PCTL) Table 4-7 defines the DSP56311 PCTL bits. Changing the following bits may cause the PLL to lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF. Table 4-7. PLL Control Register (PCTL) Bit Definitions...

  • Page 94: Bus Interface Unit (Biu) Registers

    MF[11–0] PLL Multiplication Factor Define the multiplication factor that is applied to the PLL input frequency. The MF bits are cleared during DSP56311 hardware reset and thus correspond to an MF of one. 4.6 Bus Interface Unit (BIU) Registers The three Bus Interface Unit (BIU) registers configure the external memory expansion port (Port A).
  • Page 95 When four through seven wait states are selected, one additional wait state is inserted at the end of the access. This trailing wait state increases the data hold time and the memory release time and does not increase the memory access time. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-21...

  • Page 96: Dram Control Register (Dcr)

    DRAM Control Register (DCR). The DRAM Control Register (DCR) is a 24-bit read/write register that controls and configures the external DRAM accesses. The DCR bits are shown in Figure 4-7. DSP56311 User’s Manual, Rev. 2 4-22 Freescale Semiconductor...
  • Page 97 If BREN is set and a STOP instruction is executed, periodic refresh is not generated and the refresh counter is disabled. The contents of the DRAM are lost. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-23...
  • Page 98 00 = 1 wait state for each in-page access 01 = 2 wait states for each in-page access 10 = 3 wait states for each in-page access 11 = 4 wait states for each in-page access DSP56311 User’s Manual, Rev. 2 4-24 Freescale Semiconductor...

  • Page 99: Address Attribute Registers (Aar[0-3])

    BNC bits, and the external address space (X data, Y data, or program) is enabled by the AAR. Figure 4-8 shows an AAR register; Table 4-10 lists the bit definitions. Note: The DSP56311 does not support address multiplexing. BAC11 BAC10...
  • Page 100 AA/RAS signal is active low or active high. When BAAP is cleared, the AA/RAS signal is active low (useful for enabling memory modules or for DRAM Row Address Strobe). If BAAP is set, the appropriate AA/RAS signal is active high (useful as an additional address bit). DSP56311 User’s Manual, Rev. 2 4-26 Freescale Semiconductor...

  • Page 101: Dma Control Registers 5-0 (Dcr[5-0])

    DMA transfer in some of the transfer modes defined by the DTM bits. If software explicitly clears DE during a DMA operation, the channel operation stops only after the current DMA transfer completes (that is, the current word is stored into the destination). DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-27...
  • Page 102 Note: When DTM[2–0] = 001 or 101, some peripherals can generate a second DMA request while the DMA controller is still processing the first request (see the description of the DRS bits). DSP56311 User’s Manual, Rev. 2 4-28 Freescale Semiconductor...
  • Page 103 Arbitration uses the current active DMA priority, the core priority defined by the SR bits CP[1–0], and the core-DMA priority defined by the OMR bits CDP[1–0]. Priority of core accesses to external memory is as follows: DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-29...
  • Page 104 However, if a refresh cycle from the DRAM controller is requested, the refresh cycle interrupts the DMA transfer. When DCON is cleared, the priority algorithm operates as for the DPR bits. DSP56311 User’s Manual, Rev. 2 4-30 Freescale Semiconductor...
  • Page 105 Three-Dimensional Mode Indicates whether a DMA channel is currently using three-dimensional (D3D = 1) or non-three-dimensional (D3D = 0) addressing modes. The addressing modes are specified by the DAM bits. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 4-31...

  • Page 106: Device Identification Register (Idr)

    Figure 4-10 shows the contents of the IDR. Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, and so on. Reserved Revision Number Derivative Number $317 Figure 4-10. Identification Register Configuration (Revision A) DSP56311 User’s Manual, Rev. 2 4-32 Freescale Semiconductor...

  • Page 107: Jtag Identification (Id) Register

    Figure 4-11. JTAG Identification Register Configuration (Revision 0) 4.10 JTAG Boundary Scan Register (BSR) The BSR in the DSP56311 JTAG implementation contains bits for all device signals, clock pins, and their associated control signals. All DSP56311 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR.
  • Page 108 Core Configuration DSP56311 User’s Manual, Rev. 2 4-34 Freescale Semiconductor...

  • Page 109: Programming The Peripherals

    This chapter presents general guidelines for initializing the peripherals. These guidelines include a description of how the control registers are mapped in the DSP56311, data transfer methods that are available when the various peripherals are used, and information on General-Purpose Input/Output (GPIO) configuration.

  • Page 110: Reading Status Registers

    For example, the HI08 has a host status register with two host flag bits that can be encoded by the host to generate an interrupt in the DSP. 5.4 Data Transfer Methods Peripheral I/O on the DSP56311 can be accomplished in three ways: Polling Interrupts DSP56311 User’s Manual, Rev.

  • Page 111: Polling

    One example would be setting an overflow flag in one of the Timers. Once the event occurs, the DSP56311 is free to continue with its next task. However, while it is waiting for the event to occur, the DSP56311 core is not executing any other code.

  • Page 112: Dma

    I/O in any combination without the intervention of the DSP56311 core. Dedicated DMA address and data buses and internal memory partitioning ensure that a high level of isolation is achieved so the DMA operation does not interfere with the core operation or slow it down.

  • Page 113: Advantages And Disadvantages

    5.4.4 Advantages and Disadvantages Polling is the easiest method to implement, but it requires a large amount of DSP56311 core processing power. The core cannot be involved in other processing activities while it is polling receive and transmit ready bits.

  • Page 114: General-Purpose Input/Output (Gpio)

    Programming the Peripherals 5.5 General-Purpose Input/Output (GPIO) The DSP56311 provides 34 bidirectional signals that can be configured as GPIO signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The control register settings of the DSP56311 peripherals determine whether these signals function as GPIO or as peripheral dedicated signals.

  • Page 115: Port C Signals And Registers

    Each of the three Port E signals not used as an SCI signal can be configured as a GPIO signal. Three registers control the GPIO functionality of Port E: Port E control register (PCRE), Port E DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 116: Triple Timer Signals And Registers

    GPIO signal. Each signal is controlled by the appropriate timer control status register (TCSR[0–2]). Chapter 9, Triple Timer Module, discusses these registers. DSP56311 Timer GPIO TIO0 TIO0 Timers TIO1 TIO1 TIO2 TIO2 Figure 5-6. Triple Timer Signals DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 117: Host Interface (Hi08)

    DSP core interfaces. 6.1.1 DSP Core Interface Mapping: Registers are directly mapped into eight internal X data memory locations. Data word: DSP56311 24-bit (native) data words are supported, as are 8-bit and 16-bit words. Handshaking protocols: —...
  • Page 118 • HC11 • Hitachi H8 • 8051 family • Thomson P6 family — Minimal glue logic (pull-ups, pull-downs) required to interface to • ISA bus • Freescale 68K family • Intel X86 family DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 119: Host Port Signals

    HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set. For details, see Section 6.6.3, Host Data Direction Register (HDDR), on page 6-14 and Section 6.6.4, Host Data Register (HDR), on page 6-15. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 120: Overview

    CVR = Command Vector Register RXL = Receive Register Low IVR = Interrupt Vector Register TXH = Transmit Register High TXM = Transmit Register Middle TXL = Transmit Register Low Figure 6-1. HI08 Block Diagram DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 121: Operation

    The host can then use any of the available handshaking protocols to determine whether more data is ready to be read. The DSP56311 HI08 port offers the following handshaking protocols for data transfers with the host:...

  • Page 122: Software Polling

    DSP-side HSR Host Flag bits (HSR[4–3] = HF[1–0]). 6.4.2 Core Interrupts and Host Commands The HI08 can request interrupt service from the DSP56311 core. The DSP56311 core interrupts are internal and do not require the use of an external interrupt signal. When the appropriate...
  • Page 123 DSP interrupt routines for execution. For example, the host may issue a command via the HI08 that sets up and enables a DMA transfer. The DSP56311 processor has reserved interrupt vector addresses for application-specific service routines. However, this flexibility is independent of the data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt handler (for example, SSI, SCI, IRQx, and so on).

  • Page 124: Core Dma Access

    (HREQ). Setting the ICR[2] = HDRQ bit enables both transmit and request lines to be used. Further, the host uses the ICR Receive Request Enable bit (ICR[0] = RREQ) and the ICR Transmit Request Enable bit (ICR[1] = TREQ) to enable receive and transmit requests, DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 125: Endian Modes

    The Host Little Endian bit in the host-side Interface Control Register (ICR[5] = HLEND) allows the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian mode (HLEND = 1), a host transfer occurs as shown in Figure 6-4. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 126 Little Endian bit (ICR[5] = HLEND). Big Endian mode is depicted in Figure 6-5. HTX/HRX Register: 23 DSP side Host side Low Byte High Byte (read/write last!) Host bus address: Host 32-bit internal register Figure 6-5. HI08 Read and Write Operations in Big Endian Mode DSP56311 User’s Manual, Rev. 2 6-10 Freescale Semiconductor...

  • Page 127: Boot-Up Using The Hi08 Host Port

    Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Direct memory mapping allows the DSP56311 core to communicate with the HI08 registers using standard instructions and DSP56311 User’s Manual, Rev. 2...

  • Page 128: Host Control Register (Hcr)

    Host Interface (HI08) addressing modes. In addition, the MOVEP instruction allows direct data transfers between DSP56311 internal memory and the HI08 registers or vice versa. There are two types of host processor registers, data and control, with eight registers in all. The DSP core can access all eight registers, but the external host cannot.

  • Page 129: Host Status Register (Hsr)

    —Reserved bit; read as 0; write to 0 for future compatibility. Figure 6-7. Host Status Register (HSR) (X:$FFFFC3) Table 6-9. Host Status Register (HSR) Bit Definitions Bit Number Bit Name Reset Value Description 15–5 Reserved. Write to 0 for future compatibility. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-13...

  • Page 130: Host Data Direction Register (Hddr)

    If Bit DRxx is cleared, the corresponding HI08 signal is configured as an input signal. Hardware and software reset clear the HDDR bits. DR15 DR14 DR13 DR12 DR11 DR10 DR9 Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8) DSP56311 User’s Manual, Rev. 2 6-14 Freescale Semiconductor...

  • Page 131: Host Data Register (Hdr)

    Bit Name Reset Value Description 15–8 Reserved. Write to 0 for future compatibility. 7–0 BA[10–3] Base Address Reflect the base address where the host-side registers are mapped into the bus address space. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-15...

  • Page 132: Host Port Control Register (Hpcr)

    —Reserved bit, read as 0; write to 0 for future compatibility. Figure 6-12. Host Port Control Register (HPCR) (X:$FFFFC4) To assure proper operation of the DSP56311, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. Similarly, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and HA8EN should not be set when HEN is set nor at the time HEN is set.
  • Page 133 If HEN is set, the HI08 operates as the host interface. If HEN is cleared, the HI08 is not active, and all the HI08 signals are configured as GPIO signals according to the value of the HDDR and HDR. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-17...
  • Page 134 Enables/disables signals configured as GPIO. If this bit is cleared, signals configured as GPIO are disconnected: outputs are high impedance, inputs are electrically disconnected. Signals configured as HI08 are not affected by the value of HGEN. DSP56311 User’s Manual, Rev. 2 6-18 Freescale Semiconductor...
  • Page 135 Write Data In Write Cycle Data Read Data Out Read Cycle In dual-strobe mode, separate HRD and HWR signals specify the access as a read or write access, respectively. Figure 6-14. Dual-Strobe Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-19...

  • Page 136: Host Transmit (Htx) Register

    The transfer operation sets both ISR[TXDE] and HSR[HRDF]. When the HSR[HRDF] is set, the HRX register contains valid data. The DSP56311 can set the HCR[HRIE] to cause a host receive data interrupt when HSR[HRDF] is set. When the DSP56311 reads the HRX register, the HSR[HRDF] bit is cleared.

  • Page 137: Host Programmer Model

    Selects the direction of the data transfer. If it is writing, the host processor places the data on the bus. Otherwise, the HI08 places the data on the bus. Strobes the data transfer. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-21...

  • Page 138: Interface Control Register (Icr)

    If full handshake is not needed, the host processor can treat the DSP56311 as a fast device, and data can be transferred between the host processor and the DSP56311 at the fastest data rate of the host processor.
  • Page 139 Host Flag 1 A general-purpose flag for host-to-DSP communication. The host processor can set or clear HF1, and the DSP56311 can not change it. HF1 is reflected in the HSR on the DSP side of the HI08. Host Flag 0 A general-purpose flag for host-to-DSP communication.

  • Page 140: Command Vector Register (Cvr)

    (HREQ or HRRQ) is asserted. 6.7.2 Command Vector Register (CVR) The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56311 to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI08.

  • Page 141: Interface Status Register (Isr)

    The host processor uses the HC bit to handshake the execution of host command interrupts. Normally, the host processor sets HC to request a host command interrupt from the DSP56311. When the DSP56311 acknowledges the host command interrupt, HI08 hardware clears the HC bit.
  • Page 142 DSP side of the HI08. This feature has many applications. For example, if the host processor issues a host command that causes the DSP56311 to read the HRX, the host processor can be guaranteed that the data it just transferred to the HI08 is that being received by the DSP56311.

  • Page 143: Interrupt Vector Register (Ivr)

    Receive Data Register Full Indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP56311 to be read by the host processor. RXDF is set when the HTX is transferred to the receive byte registers. RXDF is cleared when the host processor reads the receive data register (RXL or RXH according to HLEND bit).

  • Page 144: Transmit Data Registers (Txh:txm:txl)

    STOP instruction. Table 6-18. Host-Side Registers After Reset Reset Type Register Register Name Data Individual Reset STOP Reset Reset All bits — — HV[0–6] — — DSP56311 User’s Manual, Rev. 2 6-28 Freescale Semiconductor...

  • Page 145: Programming Model Quick Reference

    Line 8 Enable HA8/A1 = HA8 HA9EN Host Address HA9/A2 = GPIO — — Line 9 Enable HA9/A2 = HA9 HCSEN Host Chip Select HCS/A10 = GPIO — — Enable HCS/A10 = HCS DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-29...
  • Page 146 The Transmit Data Register is Data Empty empty. The Transmit Data Register is not empty. Host Command no host command pending Pending host command pending Host Flag 0 — — Host Flag 1 — — DSP56311 User’s Manual, Rev. 2 6-30 Freescale Semiconductor...
  • Page 147 Host Flag 0 — — Host Flag 1 — — HLEND Host Little Endian Big Endian order — — Little Endian order INIT Initialize Reset data paths according to — — TREQ and RREQ DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 6-31...
  • Page 148 Host Command no host command pending host command pending RXH/M/ 7–0 Host Receive Data Register empt TXH/M/ 7–0 Host Transmit Data empt Register 7–0 IV[7–0] Interrupt Register 68000 family vector register — — DSP56311 User’s Manual, Rev. 2 6-32 Freescale Semiconductor...

  • Page 149: Enhanced Synchronous Serial Interface (Essi)

    The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. There are two independent and identical ESSIs in the DSP56311: ESSI0 and ESSI1. For simplicity, a single generic ESSI is described here. The ESSI block diagram is shown in Figure 7-1.

  • Page 150: Essi Enhancements

    TX0 shift register. With an internally-generated bit clock, the signal becomes a high impedance output signal for a full clock period after the last data bit is transmitted if another data word does not follow immediately. If sequential data words are DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 151: Serial Receive Data Signal (Srd)

    Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as an output, functions as the serial Output Flag 0 (OF0) or as a receive shift register clock DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 152: Serial Control Signal (Sc1)

    Serial Control Direction 1 CRB[SCD1] bit determines its direction. Table 7-2. Mode and Signal Definitions Control Bits ESSI Signals F0/U F1/T0D/U F0/U F0/U F1/T0D/U F1/T0D/U F0/U F1/T0D/U DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 153: Serial Control Signal (Sc2)

    Asynchronous mode and for both the transmitter and receiver when in Synchronous mode. can be programmed as a GPIO signal ( ) when the ESSI function is not in use. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 154: Operation

    Enable the ESSI by setting the PCR bits to activate the input/output signals to be used. Write initial data to the transmitters that are in use during operation. This step is needed even if DMA services the transmitters. Enable the transmitters and receiver to be used. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 155: Exceptions

    TSR to clear the pending interrupt. ESSI transmit last slot interrupt: Occurs when the ESSI is in Network mode at the start of the last slot of the frame. This DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 156 Since step 2c may cause an immediate transmit without generating an interrupt, perform the transmit data preload in step 2b before step 2c to ensure that valid data is sent in the first transmission. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 157: Operating Modes: Normal, Network, And On-Demand

    DC[4–0] = $00000 in the CRA) with WL[2–0] = 100, the transmission does not work properly. To ensure correct operation, do not use On-Demand mode with the WL[2–0] = 100 32-bit word length mode. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 158: Synchronous/Asynchronous Operating Modes

    (for example, codec) and transmitted to a different type of device. CRB[FSL0] controls whether RX and TX have the same frame sync length. If CRB[FSL0] is cleared, both RX and TX have the same frame sync length. DSP56311 User’s Manual, Rev. 2 7-10 Freescale Semiconductor...

  • Page 159: Word Length Frame Sync And Data Word Timing

    MSB first. If CRB[SHFD] is set, data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-11...

  • Page 160: Flags

    The value on SC[1–0] is stable from the time the first bit of the transmit data word transmits until the first bit of the next transmit data word transmits. Software can directly set the OF[1–0] values, allowing the DSP56311 to control data transmission by indirectly controlling the value of the SC[1–0] flags.

  • Page 161: Essi Control Register A (Cra)

    Synchronous mode (SYN = 1), and transmitter 2 is disabled (TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is configured as output (SCD1 = 1). DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-13...
  • Page 162 If the ALC bit is set, only 8-, 12-, or 16-bit words are used. The use of 24- or 32-bit words leads to unpredictable results. Reserved. Write to 0 for future compatibility. DSP56311 User’s Manual, Rev. 2 7-14 Freescale Semiconductor...
  • Page 163 SSI in other DSP56000 family members. The maximum allowed internally generated bit clock frequency is the internal DSP56311 clock frequency divided by 4; the minimum possible internally generated bit clock frequency is the DSP56311 internal clock frequency divided by 4096.
  • Page 164 Clock Internal TX Frame Sync Sync SCn2 /1 to /32 Type Sync: TX/RX F.S. Transmit Async: Transmit TX F.S. Control Frame Sync Logic Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram DSP56311 User’s Manual, Rev. 2 7-16 Freescale Semiconductor...

  • Page 165: Essi Control Register B (Crb)

    Network mode, if you clear the appropriate TE bit and set it again, then you disable the corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter remains disabled until the beginning of the next frame. During that time period, the DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-17...
  • Page 166 If the transmitter underrun error (TUE) bit is set (signaling that an exception has occurred) and the TEIE bit is set, the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller. DSP56311 User’s Manual, Rev. 2 7-18 Freescale Semiconductor...
  • Page 167 On-Demand mode can be the same as in Normal mode, or the TE1 bit can be left enabled. Note: The setting of the TE1 bit does not affect the generation of frame sync or output flags. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-19...
  • Page 168 When FSP is set, the frame sync signal polarity is negative; that is, the frame start is indicated by the frame sync signal going low. DSP56311 User’s Manual, Rev. 2 7-20 Freescale Semiconductor...
  • Page 169 GPIO pins as outputs or configure the pins in the PCR as ESSI signals. The default selection for these signals after reset is GPIO. This note applies to both ESSI0 and ESSI1. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-21...
  • Page 170 Data present in Bit OF0 is written to SC0 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode. DSP56311 User’s Manual, Rev. 2 7-22 Freescale Semiconductor...
  • Page 171 Mixed Frame Length: FSL1 = 1, FSL0 = 1 Serial Clock RX Frame SYNC RX Serial Data Data Data TX Frame SYNC TX Serial Data Data Data Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-23...
  • Page 172 External Frame SYNC Internal Clock Internal Frame SYNC ESSI Bit Clock Clock Frame SYNC Receiver NOTE: Transmitter and receiver may have the same clock frame syncs. Figure 7-7. CRB SYN Bit Operation DSP56311 User’s Manual, Rev. 2 7-24 Freescale Semiconductor...
  • Page 173 ESSI Programming Model Figure 7-8. CRB MOD Bit Operation DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-25...

  • Page 174: Essi Status Register (Ssisr)

    The SSISR is a read-only status register by which the DSP reads the ESSI status and serial input flags. —Reserved bit; read as 0; write to 0 0 for future compatibility. (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7) Figure 7-11. ESSI Status Register (SSISR) DSP56311 User’s Manual, Rev. 2 7-26 Freescale Semiconductor...
  • Page 175 TE0, TE1, or TE2 is set). In Normal mode, TFS is always read as 1 when data is being transmitted because there is only one time slot per frame, the frame sync time slot. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-27...

  • Page 176: Essi Receive Shift Register

    ALC bit. When ALC is cleared, the MSB is Bit 23 and the least significant byte is unused. When ALC is set, the MSB is Bit 15 and the most significant byte is DSP56311 User’s Manual, Rev. 2 7-28...
  • Page 177 (b) Transmit Registers Data is transmitted MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. Figure 7-12. ESSI Data Path Programming Model (SHFD = 0) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-29...
  • Page 178 (b) Transmit Registers Data is received MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. Figure 7-13. ESSI Data Path Programming Model (SHFD = 1) DSP56311 User’s Manual, Rev. 2 7-30 Freescale Semiconductor...

  • Page 179: Essi Transmit Data Registers (Tx[2-0])

    TS15 TS14 TS13 TS12 TS11 TS10 —Reserved bit; read as 0; write to 0 0 for future compatibility. (ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4) Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-31...
  • Page 180 The frame being transmitted is not affected by the new TSM setting. If the TSM is read, it shows the current setting. After a hardware signal or software RESET instruction, the TSM register is reset to RESET $FFFFFFFF, enabling all 32 slots for data transmission. DSP56311 User’s Manual, Rev. 2 7-32 Freescale Semiconductor...

  • Page 181: Receive Slot Mask Registers (Rsma, Rsmb)

    0. After a hardware signal or a software RESET instruction, the RSM register is reset to RESET $FFFFFFFF, enabling all 32 time slots for data transmission. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-33...

  • Page 182: Gpio Signals And Registers

    PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding direction bits for Port C GPIOs are PRC[5–0]. The corresponding direction bits for Port D GPIOs are PRD[5–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE) DSP56311 User’s Manual, Rev. 2 7-34 Freescale Semiconductor...

  • Page 183: Port Data Registers (Pdrc And Pdrd)

    GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 7-35...
  • Page 184 Enhanced Synchronous Serial Interface (ESSI) DSP56311 User’s Manual, Rev. 2 7-36 Freescale Semiconductor...

  • Page 185: Serial Communication Interface (Sci)

    11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop) This mode is used for master/slave operation with wake-up on idle line and wake-up on address bit capability. It allows the DSP56311 to share a single serial line efficiently with other peripherals.

  • Page 186: Synchronous Mode

    Receivers with an address match can receive the message and optionally transmit an acknowledgment to the sender. The particular message format and protocol used are determined by the user’s software. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 187: Transmitting Data And Address Characters

    SCI functions. In this case, only one transmit interrupt can be generated because the Transmit Data Register is empty. The timer and timer interrupt operate regardless of how the SCI pins are configured, either as SCI or GPIO. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 188: Receive Data (Rxd)

    During individual reset, internal DMA accesses to the data registers of the SCI are not valid, and the data is unknown. Stop processing state reset (that is, the STOP instruction) Executing the STOP instruction halts operation of the SCI until the DSP is restarted, DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 189 Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO). Stop reset is caused by executing the STOP instruction. The bit is set during this reset. The bit is cleared during this reset. — The bit is not changed during this reset. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 190: Sci Initialization

    The DMA channel services the SCI transmit request if it is programmed to service the SCI transmitter. Enable transmitters (TE = 1) and receiver (RE = 1) according to use. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 191: Preamble, Break, And Data Transmission Priority

    The next step is to receive the program size and then the starting address to load the program. These two numbers are three bytes each loaded least significant byte first. Each byte is echoed DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 192: Exceptions

    — SCI Clock Control Register (SCCR) in Figure 8-4 Status — SCI Status Register (SSR) in Figure 8-3 Data transfer — SCI Receive Data Registers (SRX) in Figure 8-7 — SCI Transmit Data Registers (STX) in Figure 8-7 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 193 • D0 = LSB; D7 = MSB • Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 194: Sci Control Register (Scr)

    MSB first if SSFTD = 1. Figure 8-2. SCI Data Word Formats (SSFTD = 0), 2 8.6.1 SCI Control Register (SCR) The SCR is a read/write register that controls the serial interface operation. DSP56311 User’s Manual, Rev. 2 8-10 Freescale Semiconductor...
  • Page 195 16 (to match the 1 × SCI baud rate) for timer interrupt generation. This timer does not require that any SCI signals be configured for SCI use to operate. Either a hardware RESET signal or a software RESET instruction clears TMIE. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 8-11...
  • Page 196 If the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission, the transmit data line remains idle until STX is finally written. DSP56311 User’s Manual, Rev. 2 8-12 Freescale Semiconductor...
  • Page 197 11-bit asynchronous with parity modes. Thus, the received character is an address that has to be processed by all sleeping processors—that is, each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 8-13...
  • Page 198 (1 start, 8 data, 1 even parity, 1 stop) 11-Bit Asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 11-Bit Multidrop Asynchronous (1 start, 8 data, 1 data type, 1 stop) Reserved DSP56311 User’s Manual, Rev. 2 8-14 Freescale Semiconductor...

  • Page 199: Sci Status Register (Ssr)

    8-bit Synchronous mode, the PE bit is always cleared since there is no parity bit in these modes. If the byte received causes both parity and overrun errors, the SCI receiver recognizes only the overrun error. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 8-15...
  • Page 200 STX or STXA is transmitted next. That is, there is no word in the transmit shift register being transmitted. This procedure is useful when initiating the transfer of a message (that is, a string of characters). DSP56311 User’s Manual, Rev. 2 8-16 Freescale Semiconductor...

  • Page 201: Sci Clock Control Register (Sccr)

    11–0 CD[11–0] Clock Divider Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide ratio from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 8-17...
  • Page 202 It must use the same source for both the TX and RX clock. The internal clock is used if the SCI is the master device DSP56311 User’s Manual, Rev. 2 8-18 Freescale Semiconductor...

  • Page 203: Sci Data Registers

    There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX or STXA) and a parallel-to-serial Transmit Shift Register. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 8-19...

  • Page 204: Sci Receive Register (Srx)

    24-bit word by ORing three data bytes read from the three addresses. The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial word. The SCR receive clock mode (RCM) defines the clock source. DSP56311 User’s Manual, Rev. 2 8-20 Freescale Semiconductor...

  • Page 205: Sci Transmit Register (Stx)

    MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order. The data to be transmitted can be written to any one of the three STX DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 206: Gpio Signals And Registers

    For bits 2–0, a 0 selects PEn as the signal and a 1 selects the specified SCI signal. = Reserved. Read as zero. Write to zero for future compatibility. Figure 8-8. Port E Control Register (PCRE X:$FFFF9F) DSP56311 User’s Manual, Rev. 2 8-22 Freescale Semiconductor...

  • Page 207: Port E Direction Register (Prre)

    GPIO signal by the PCRE bits. For SCI, the GPIO signals are PE[2–0]. The corresponding data bits are PDRE[2–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 8-10. Port Data Registers (PDRE X:$FFFF9D) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 8-23...
  • Page 208 Serial Communication Interface (SCI) DSP56311 User’s Manual, Rev. 2 8-24 Freescale Semiconductor...

  • Page 209: Triple Timer Module

    Triple Timer Module The timers in the DSP56311 internal triple timer module act as timed pulse generators or as pulse-width modulators. Each timer has a single signal that can function as a GPIO signal or as a timer signal. Each timer can also function as an event counter to capture an event or to measure the width or period of a signal.

  • Page 210: Individual Timer Block Diagram

    Figure 9-1. Triple Timer Module Block Diagram 9.1.2 Individual Timer Block Diagram Figure 9-2 shows the structure of an individual timer block. The DSP56311 treats each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space.

  • Page 211: Operation

    Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE] bit. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt enable bits as needed for the application. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 212: Timer Exceptions

    Enable and prioritize overall peripheral interrupt functionality. IPRP (TOL[1–0]) Enable a specific peripheral interrupt. TCSR0 (TCIE) Unmask interrupts at the global level. SR (I[1–0]) Configure a peripheral interrupt-generating function. TCSR0 (TC[7–4]) Enable peripheral and associated signals. TCSR0 (TE) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 213: Operating Modes

    In Mode 0, the timer generates an internal interrupt when a counter value is reached, if the timer compare interrupt is enabled (see Figure 9-3 and Figure 9-4). When the counter equals the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 214 (CLK/2 or prescale CLK) N + 1 M + 1 Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) TOF (Overflow Interrupt if TCIE = 1) Figure 9-4. Timer Mode (TRM = 0) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 215: Timer Pulse (Mode 1)

    Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) TIO pin (INV = 0) pulse width = timer clock period TIO pin (INV = 1) Figure 9-5. Pulse Mode (TRM = 1) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 216: Timer Toggle (Mode 2)

    TIO signal. To generate output signals with a delay of X clock cycles between toggles, set the TLR value to X/2, and set the TCSR[TRM] bit. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared). DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 217 First toggle = M - N clock periods Second and later toggles = 2 clock periods TIO pin (INV = 1) TOF (Overflow Interrupt if TCIE = 1) Figure 9-8. Toggle Mode, TRM = 0 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 218: Timer Event Counter (Mode 3)

    TIO input signal or the prescaler clock output. If an external clock is used, it must be internally synchronized to the internal clock, and its frequency must be less than the DSP56311 internal operating frequency divided by 4. The value of the TCSR[INV] bit determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter.

  • Page 219: Signal Measurement Modes

    The external signal synchronizes with the internal clock that increments the counter. This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-11...

  • Page 220: Measurement Input Width (Mode 4)

    NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO stops the counter and loads TCR with the count. Figure 9-11. Pulse Width Measurement Mode, TRM = 1 DSP56311 User’s Manual, Rev. 2 9-12 Freescale Semiconductor...

  • Page 221: Measurement Input Period (Mode 5)

    TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter and enable the timer. The counter is repeatedly loaded and incremented until the timer is disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it overflows. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-13...
  • Page 222 NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO loads TCR with count and the counter with N. Figure 9-14. Period Measurement Mode, TRM = 0 DSP56311 User’s Manual, Rev. 2 9-14 Freescale Semiconductor...

  • Page 223: Measurement Capture (Mode 6)

    TCF (Compare Interrupt if TCIE = 1) periods NOTE: If INV = 1, a 1-to-0 edge on TIO loads TCR with count and stops the counter. Figure 9-15. Capture Measurement Mode, TRM = 0 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-15...

  • Page 224: Pulse Width Modulation

    The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF − TLR + 1). For a 50 percent duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1)/2. Note: The value in TCPR must be greater than the value in TLR. DSP56311 User’s Manual, Rev. 2 9-16 Freescale Semiconductor...
  • Page 225 TCF (Compare Interrupt if TCIE = 1) TCF (Overflow Interrupt if TDIE = 1) TIO pin (INV = 0) TIO pin (INV = 1) Pulse width Period Figure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-17...

  • Page 226: Watchdog Modes

    NOTE: On overflow, TCR is loaded with the value of TLR. Figure 9-17. Pulse Width Modulation Toggle Mode, TRM = 0 9.3.4 Watchdog Modes The following watchdog timer modes are provided: Watchdog Pulse Watchdog Toggle DSP56311 User’s Manual, Rev. 2 9-18 Freescale Semiconductor...

  • Page 227: Watchdog Pulse (Mode 9)

    TIO can connect to the RESET pin, internal hardware preserves the TIO value and direction for an additional 2.5 clocks to ensure a reset of valid length. Figure 9-18. Watchdog Pulse Mode DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-19...

  • Page 228: Watchdog Toggle (Mode 10)

    TIO can connect to the RESET pin, internal hardware preserves the TIO value and direction for an additional 2.5 clocks to ensure a reset of valid length. Figure 9-19. Watchdog Toggle Mode 9.3.4.3 Reserved Modes Modes 8, 11, 12, 13, 14, and 15 are reserved. DSP56311 User’s Manual, Rev. 2 9-20 Freescale Semiconductor...

  • Page 229: Special Cases

    DSP56311 is in stop state. To ensure correct operation, disable the timers before the DSP56311 is placed in stop state. 9.3.6 DMA Trigger Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event.

  • Page 230: Timer Prescaler Load Register (Tplr)

    PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 PL11 PL10 — Reserved bit. Read as 0. Write to 0 for future compatibility Figure 9-21. Timer Prescaler Load Register (TPLR) DSP56311 User’s Manual, Rev. 2 9-22 Freescale Semiconductor...

  • Page 231: Timer Prescaler Count Register (Tpcr)

    If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56311 internal operating frequency divided by 4 (that is, CLK/4). Note: To ensure proper operation, change the PS[1–0] bits only when the...

  • Page 232: Timer Control/Status Register (Tcsr)

    PS[1–0] bits of the TPLR determine which source clock is used for the prescaler. A timer can be clocked by a prescaler clock that is derived from the TIO of another timer. Reserved. Write to zero for future compatibility. DSP56311 User’s Manual, Rev. 2 9-24 Freescale Semiconductor...
  • Page 233 (the TCSR[TE] bit is cleared). The timer is in GPIO mode. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-25...
  • Page 234 — Reserved — — Reserved — — Reserved — — Note: The GPIO function is enabled only if all of the TC[3–0] bits are 0. Reserved. Write to zero for future compatibility. DSP56311 User’s Manual, Rev. 2 9-26 Freescale Semiconductor...
  • Page 235 Width of the low input pulse is measured. measured. — — Period is measured between Period is measured between the rising edges of the input the falling edges of the input signal. signal. — — DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-27...

  • Page 236: Timer Load Register (Tlr)

    (that is, the timer compare interrupt enable bit in the TCSR is set). The TCPR is ignored in measurement modes. DSP56311 User’s Manual, Rev. 2 9-28 Freescale Semiconductor...

  • Page 237: Timer Count Register (Tcr)

    When the timer is in measurement mode, the signal is used for the input signal. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor 9-29...
  • Page 238 Triple Timer Module DSP56311 User’s Manual, Rev. 2 9-30 Freescale Semiconductor...

  • Page 239: Enhanced Filter Coprocessor

    — K-constant input register for coefficient updates (in adaptive mode) IIR filter options: — Direct form 1 (DFI) and direct form 2 (DFII) configurations — Three optional output scaling factors (1, 8, or 16) DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-1...

  • Page 240: Architecture Overview

    — Data input buffer — Constant input buffer — Output buffer — Filter counter Filter data memory (FDM) bank Filter coefficient memory (FCM) bank Filter multiplier accumulator (FMAC) machine Address generator Control logic DSP56311 Reference Manual, Rev. 2 10-2 Freescale Semiconductor...

  • Page 241: Pmb Interface

    EFCOP address generation logic to generate correct addressing to the FDM and FCM. EFCOP Control Status A 24-bit read/write register used by the DSP56300 core to program the EFCOP and to examine Register (FCSR) the status of the EFCOP module. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-3...

  • Page 242: Efcop Memory Banks

    FCM register as shown in Figure 10-2. D(0) H(N - 1) D(1) H(N - 2) D(2) Data D(3) Coefficient Memory Memory D(4) Bank Bank D(5) (FDM) (FCM) H(1) H(0) Figure 10-2. Storage of Filter Coefficients DSP56311 Reference Manual, Rev. 2 10-4 Freescale Semiconductor...

  • Page 243: Filter Multiplier And Accumulator (Fmac)

    ($7FFF, if overflow occurred) or the most negative number ($8000, if underflow occurred) after processing of all filter taps is completed. In saturation mode, the result is limited to the most positive number ($7FFF, if overflow occurred) or the most negative number ($8000, DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-5...
  • Page 244 EFCOP output buffer, FDOR. 10.3 EFCOP Operation DSP56311 EFCOP operation is determined by the control bits in the EFCOP Control/Status Register (FCSR), described in Section 10.4.5. Further filtering operations are enabled via the appropriate bits in the FACR and FDCH registers. After the FCSR is configured to the mode of choice, enable the EFCOP by setting FCSR[FEN].

  • Page 245: Efcop Operation

    Initialization is always disabled with the IIR filter type, and the FCSR[FPRC] bit is ignored. Thus, the DSP56300 core must write the initial input values before the EFCOP is enabled. The first value written to FDIR is always the first sample to be filtered. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-7...

  • Page 246: Fir Filter Type

    FCSR. One sample, the real input, is written to the FDIR, and the EFCOP processes the data. Then one sample, the real output, is read from the FDOR. Four options are available with the real FIR filter type: coefficient update, adaptive mode, multichannel mode, and decimation. The first DSP56311 Reference Manual, Rev. 2 10-8 Freescale Semiconductor...

  • Page 247: Complex Mode

    FDOR. Alternating Complex mode is selected by setting the FCSR[FOM] bits to 10. In Alternating Complex mode, the number written to the FCNT register should be twice the number of filter DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-9...

  • Page 248: Magnitude Mode

    EFCOP halts processing until a value is written to the FKIR. When a value is written to the FKIR, the EFCOP updates all the coefficients based on the above equation using the value in the DSP56311 Reference Manual, Rev. 2 10-10...

  • Page 249: Multichannel Mode Option

    10-5 based on the equation shown here. The EFCOP multiplies each previous output value in the ⎛ ⎞ ⎜ ⎟ ∑ y n ( ) S w n ( ) y n j – ⎜ ⎟ ⎝ ⎠ DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-11...

  • Page 250: Efcop Data Transfer Examples

    Here, we provide background information to help you understand the examples in Section 10.3.6, EFCOP Operation Examples, on page 10-14. The examples employ the following notations: D(n): Data sample at time n H(n): Filter coefficient at time n DSP56311 Reference Manual, Rev. 2 10-12 Freescale Semiconductor...
  • Page 251 The filter coefficient bank must therefore be initialized before an input data transfer starts. The DMA input channel DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-13...

  • Page 252: Efcop Operation Examples

    Set the operation mode (FCSR[5:4] = FOM[00]). Set Initialization mode (FCSR[7] = FPRC = 0). 1. For information on DMA transfers, refer to the Freescale application note entitled Using the DSP56300 Direct Memory Access Controller (APR23/D). DSP56311 Reference Manual, Rev. 2 10-14 Freescale Semiconductor...
  • Page 253 DCR1 bit values are as follows: DMA Control Register 1 DIE = 0 Disables end-of-transfer interrupt. DTM = 1 Chooses word transfer triggered by request, DE auto clear on end of transfer. DPR = 3 Priority 3. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-15...
  • Page 254 DMA input to transfer up to four new data words to FDIR. • Compute F(n); The result is stored in FDOR, and this triggers the DMA for an output data transfer. DSP56311 Reference Manual, Rev. 2 10-16 Freescale Semiconductor...
  • Page 255 ; number of outputs generated. FDBA_ADDRS 0 ; Input samples Start Address x:$0 FCBA_ADDRS 0 ; Coeff. Start Address y:$0 ;;****************************************************************** ; main program ;;****************************************************************** ORG p:Start move#FDBA_ADDRS,r0 ; FDM memory area move#0,x0 rep #DST_COUNT DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-17...
  • Page 256 #$1,x:M_DOR0 ; DMA offset reg. is 1. movep #$94AA04,x:M_DCR0 ; Init DMA control reg to line mode FDIBE request. ;;****************************************************************** jclr #0,x:M_DSTR,* jclr #1,x:M_DSTR,* stop_label jmp stop_label org x:SRC_ADDRS INCLUDE ‘input.asm’ org y:FCBA_ADDRS INCLUDE ‘coefs.asm’ DSP56311 Reference Manual, Rev. 2 10-18 Freescale Semiconductor...

  • Page 257: Dma Input/Polling Output

    $3000; address at which to begin output SRC_COUNT $006003 ; DMA0 count (7*4 word transfers) DST_COUNT ; number of outputs generated. FDBA_ADDRS 0 ; Input samples Start Address x:$0 FCBA_ADDRS 0 ; Coeff. Start Address y:$0 ;;****************************************************************** DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-19...
  • Page 258 #SRC_COUNT,x:M_DCO0 ; Init DMA count to line mode. movep #$1,x:M_DOR0 ; DMA offset reg. is 1. movep #$94AA04,x:M_DCR0 ; Init DMA control reg to line mode FDIBE request. ;;****************************************************************** #DST_COUNT,endd jclr #15,y:M_FCSR,* movep y:M_FDOR,x:(r0)+ endd stop_label DSP56311 Reference Manual, Rev. 2 10-20 Freescale Semiconductor...

  • Page 259: Dma Input/Interrupt Output

    Example 10-3. Real FIR Filter DMA Input/Interrupt Output INCLUDE 'ioequ.asm' ;;****************************************************************** ; equates ;;****************************************************************** Startequ$00100; main program starting address FCON equ $801 ; EFCOP FSCR register contents: DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-21...
  • Page 260 #0,a move #DST_COUNT,b0 ; counter for output interrupt move#FDBA_ADDRS,r0 ; FDM memory area move#0,x0 rep #DST_COUNT movex0,x:(r0)+ ; clear FDM memory area move #DST_ADDRS,r0 ; Destination address ; ** EFCOP initialization ** DSP56311 Reference Manual, Rev. 2 10-22 Freescale Semiconductor...
  • Page 261 ;;****************************************************************** ; Interrupt handler for EFCOP output movep y:M_FDOR,x:(r0)+ ; Get y(k) from FDOR ; Store in destination memory space. dec b jne cont bclr #11,y:M_FCSR ; Disable output interrupt cont DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-23...

  • Page 262: Real Fir Filter With Decimation By M

    H(N - 2) Stream D(2) F(0) Data D(3) Coefficient F(M) Memory Memory D(4) Bank Bank F(2M) D(5) (FDM) (FCM) F(3M) H(1) H(0) F(4M) Figure 10-7. Real FIR Filter Data Stream With Decimation by M DSP56311 Reference Manual, Rev. 2 10-24 Freescale Semiconductor...

  • Page 263: Adaptive Fir Filter

    R(n) is the desired signal at time n. This stage requires a single arithmetic operation. Stage 3. The core calculates the weight multiplier, Ke(n), in software according to the following equation: K e (n) = K * E(n) DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-25...

  • Page 264: Implementation Using Polling

    FKIR (ADP) Real FIR Mode Write next x(n) Set FUPD = 1 (opt.) Automatically Done in ADP Mode Output Buffer Full? Read y(n) Block Done? Figure 10-9. Adaptive FIR Filter Using Polling DSP56311 Reference Manual, Rev. 2 10-26 Freescale Semiconductor...

  • Page 265: Implementation Using Dma Input And Interrupt Output

    Example 10-4. FIR Adaptive Filter Update Using the LMS Algorithm TITLE 'ADAPTIVE' INCLUDE 'ioequ.asm' ;;************************************************************************************ ; equates ;;************************************************************************************ Start $00100 ; main program starting address FCON $805 ; EFCOP FSCR register contents: DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-27...
  • Page 266 >kdo ;;************************************************************************************ ; main program ;;************************************************************************************ ORG p:Start ; ** interrupt initialization ** bset #10,x:M_IPRP bset #11,x:M_IPRP ; enable EFCOP interrupts in IPRP bclr #8,SR bclr #9,SR ; enable interrupts in SR DSP56311 Reference Manual, Rev. 2 10-28 Freescale Semiconductor...
  • Page 267 ; Init DMA destination address. movep #SRC_COUNT,x:M_DCO0 ; Init DMA count to line mode. movep #$1,x:M_DOR0 ; DMA offset reg. is 1. movep #$94AA04,x:M_DCR0 ; Init DMA control reg to line mode FDIBE request. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-29...
  • Page 268 ; Retrieve desired value R(n) move x:(r0)+,y0 y0,a ; calculate E(n) = R(n) - F(n) move #MU2,y0 move a,y1 y0,y1,a ; calculate Ke = mu * 2 * E(n) ;****************************** movepa1,y:M_FKIR ; store Ke in FKIR DSP56311 Reference Manual, Rev. 2 10-30 Freescale Semiconductor...
  • Page 269 #11,y:M_FCSR ; Disable output interrupt cont ;;****************************************************************** ;;****************************************************************** ORG y:FCBA_ADDRS $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-31...

  • Page 270: Verification For Filter Examples

    Section 10.3.6.1 through Section 10.3.6.3. 10.3.6.4.1 Input Sequence (input.asm) $000000 $37cc8a $343fae $0b63b1 $0595b4 $38f46e $6a4ea2 $5e8562 $2beda5 $1b3cd0 $42f452 $684ca0 $5093b0 $128ab8 $f74ee1 $15c13a $336e48 $15e98e $d428d2 $b76af5 $d69eb3 $f749b6 $dee460 DSP56311 Reference Manual, Rev. 2 10-32 Freescale Semiconductor...

  • Page 271: Filter Coefficients (Coefs.asm)

    $000342 dc $02B24F dc $06C977 dc $096ADD dc $097556 dc $08FD54 dc $0A59A5 10.3.6.4.3 Output Sequence for Examples 10-1, 10-2, and 10-3 $d69ea9 $ccae36 $c48f2a $be8b28 $bad8c5 $b9998c $bad8cb $be8b2d $c7b906 DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-33...

  • Page 272: Desired Signal For Example 10-4

    $443031 $4642D6 $45D849 $42F452 $3DB126 $363E7F $2CDFE8 $21EA5B $15C13A $08D2CE $FB945D $EE7E02 $E2066F $D69EB2 $CCAE3C $C48F2F $BE8B32 $BAD8D3 $B99999 $BAD8D3 $BE8B32 10.3.6.4.5 Output Sequence for Example 10-4 $000000 $f44c4c $ee54b3 $e7cd6b $daed26 DSP56311 Reference Manual, Rev. 2 10-34 Freescale Semiconductor...

  • Page 273: Efcop Programming Model

    FDOR clears the FDOBF bit. Data transfers can be triggered by an interrupt request (for core transfers) or a DMA request (DMA transfers). The FDOR is accessible for reads by the DSP56300 core and the DMA controller. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-35...

  • Page 274: Filter K-Constant Input Register (Fkir)

    The number of coefficient values is the number of locations used in the FCM. For a real FIR filter, the number of coefficient values is identical to the number of filter taps. For a complex FIR filter, the number of coefficient values is twice the number of filter taps. DSP56311 Reference Manual, Rev. 2 10-36 Freescale Semiconductor...

  • Page 275: Efcop Control Status Register (Fcsr)

    FSAT bit is set, and the result is saturated to the most negative number (that is, $800000). FSAT is a sticky status bit that is set by hardware and can be cleared only by a hardware RESET signal, a software RESET instruction, or an individual reset. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-37...
  • Page 276 EFCOP operates in single filter mode. To ensure proper operation, never change the FMLC bit unless the EFCOP is in individual reset state (that is, FEN = 0). DSP56311 Reference Manual, Rev. 2 10-38 Freescale Semiconductor...
  • Page 277 RESET signal or a software RESET instruction; the contents of the FCNT, FDBA, and FCBA registers are preserved; and the control bits in FCSR and FACR remain unchanged. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-39...

  • Page 278: Efcop Alu Control Register (Facr)

    • FRM = 00—Convergent rounding • FRM = 01—Two’s complement rounding • FRM = 10—Truncation (no rounding) • FRM = 11—Reserved for future expansion These bits affect operation of the EFCOP data ALU. DSP56311 Reference Manual, Rev. 2 10-40 Freescale Semiconductor...

  • Page 279: Efcop Data Base Address (Fdba)

    Therefore, a FCBA read always gives the value of the lower address boundary. DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-41...

  • Page 280: Decimation/Channel Count Register (Fdch)

    0, then 1 channel is processed; if FCHL =1, then 2 channels are processed; and so on. To ensure proper operation, never change the FCHL bits unless the EFCOP is in the individual reset state (FEN = 0). DSP56311 Reference Manual, Rev. 2 10-42 Freescale Semiconductor...

  • Page 281: Efcop Interrupt Vectors

    FDOBF = 1 Table 10-11. EFCOP DMA Request Sources Peripheral Request Requesting Device Number Request Conditions MDRQ EFCOP input buffer empty FDIBE = 1 MDRQ11 EFCOP output buffer full FDOBF = 1 MDRQ12 DSP56311 Reference Manual, Rev. 2 Freescale Semiconductor 10-43...
  • Page 282 Enhanced Filter Coprocessor DSP56311 Reference Manual, Rev. 2 10-44 Freescale Semiconductor...

  • Page 283: Bootstrap Program

    Bootstrap Program This appendix lists the bootstrap program and equates for the DSP56311. Freescale posts updates to the bootstrap program on the Worldwide Web at the web site listed on the back cover of this manual. A.1 Bootstrap Code ; BOOTSTRAP CODE FOR DSP56311 - (C) Copyright 1999 Motorola Inc.
  • Page 284 ; setting the Host Flag 0 (HF0). This starts execution of the loaded ; program from the specified starting address. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1110, then the program RAM is loaded from the Host DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 285 ; where the external byte-wide ; EPROM would be located AARV $D00409 ; AAR1 selects the EPROM as CE~ ; mapped as P from $D00000 to ; $DFFFFF, active low ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 286 4 - i8051 - Dual strobe multiplexed bus with negative strobe pulses dual negative request. 5 - MC68302 - Single strobe non-multiplexed bus with negative strobe pulse single negative request. ;======================================================================== MC68302HOSTLD movep #%0000000000111000,x:M_HPCR DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 287 ; HA8EN = 0 (address 8 enable bit has no meaning non-multiplexed bus) ; HGEN = 0 Host GPIO pins are disabled <HI08CONT HC11HOSTLD movep #%0000001000011000,x:M_HPCR ; Configure the following conditions: DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 288 ; wait for the program length to be ; written movep x:M_HRX,a0 jclr #HRDF,x:M_HSR,* ; wait for the program starting address ; to be written movep x:M_HRX,r0 move r0,r1 a0,HI08LOOP ; set a loop with the downloaded length DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 289 ; Store 24-bit result in P mem. ; pipeline delay _LOOP7 bra <FINISH ; Boot from SCI done ;======================================================================== ; This is the routine that loads from external EPROM. ; MD:MC:MB:MA=1001 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 290 ; MD:MC:MB:MA=010x is reserved jclr #0,omr,RESERVED ; MD:MC:MB:MA=0110 is reserved ; MD:MC:MB:MA=0111 is reserved RESERVED <* A.2 Internal I/O Equates ;*********************************************************************** EQUATES for DSP56311 I/O registers and ports Last update: February 20 1999 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...

  • Page 291: Internal I/O Equates

    ; Host Command Interrupt Enable M_HF2 ; Host Flag 2 M_HF3 ; Host Flag 3 HSR bits definition M_HRDF ; Host Receive Data Full M_HTDE ; Host Receive Data Empty M_HCP ; Host Command Pending DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 292 M_RWU ; Receiver Wakeup Enable M_WOMS ; Wired-OR Mode Select M_SCRE ; SCI Receiver Enable M_SCTE ; SCI Transmitter Enable M_ILIE ; Idle Line Interrupt Enable M_SCRIE ; SCI Receive Interrupt Enable DSP56311 User’s Manual, Rev. 2 A-10 Freescale Semiconductor...
  • Page 293 ; SSI1 Time Slot Register M_RX1 $FFFFA8 ; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register M_CRB1 $FFFFA6 ; SSI1 Control Register B M_CRA1 $FFFFA5 ; SSI1 Control Register A DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor A-11...
  • Page 294 ; Serial Input Flag 1 M_TFS ; Transmit Frame Sync Flag M_RFS ; Receive Frame Sync Flag M_TUE ; Transmitter Underrun Error FLag M_ROE ; Receiver Overrun Error Flag M_TDE ; Transmit Data Register Empty DSP56311 User’s Manual, Rev. 2 A-12 Freescale Semiconductor...
  • Page 295 ; DMA1 Interrupt Priority Level Mask M_D1L0 ; DMA1 Interrupt Priority Level (low) M_D1L1 ; DMA1 Interrupt Priority Level (high) M_D2L $30000 ; DMA2 Interrupt priority Level Mask M_D2L0 ; DMA2 Interrupt Priority Level (low) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor A-13...
  • Page 296 Register Addresses Of TIMER1 M_TCSR1 $FFFF8B ; TIMER1 Control/Status Register M_TLR1 $FFFF8A ; TIMER1 Load Reg M_TCPR1 $FFFF89 ; TIMER1 Compare Register M_TCR1 $FFFF88 ; TIMER1 Count Register Register Addresses Of TIMER2 DSP56311 User’s Manual, Rev. 2 A-14 Freescale Semiconductor...
  • Page 297 M_DOR1 $FFFFF2 ; DMA Offset Register 1 M_DOR2 $FFFFF1 ; DMA Offset Register 2 M_DOR3 $FFFFF0 ; DMA Offset Register 3 Register Addresses Of DMA0 M_DSR0 $FFFFEF ; DMA0 Source Address Register DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor A-15...
  • Page 298 ; DMA Address Mode 0 M_DAM1 ; DMA Address Mode 1 M_DAM2 ; DMA Address Mode 2 M_DAM3 ; DMA Address Mode 3 M_DAM4 ; DMA Address Mode 4 M_DAM5 ; DMA Address Mode 5 DSP56311 User’s Manual, Rev. 2 A-16 Freescale Semiconductor...
  • Page 299 ; EFCOP Coefficient Base Address M_FDCH $FFFFB8 ; EFCOP Decimation/Channel Register ;------------------------------------------------------------------------ EQUATES for Phase Locked Loop (PLL) ;------------------------------------------------------------------------ Register Addresses Of PLL M_PCTL $FFFFFD ; PLL Control Register PLL Control Register DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor A-17...
  • Page 300 ; Refresh prescaler Address Attribute Registers M_BAT ; External Access Type and Pin Definition Bits Mask (BAT0-BAT1) M_BAAP ; Address Attribute Pin Polarity M_BPEN ; Program Space Enable M_BXEN ; X Data Space Enable DSP56311 User’s Manual, Rev. 2 A-18 Freescale Semiconductor...
  • Page 301 ; Stack Extension space select bit in OMR. M_EUN ; Extended stack UNderflow flag in OMR. M_EOV ; Extended stack OVerflow flag in OMR. M_WRP ; Extended WRaP flag in OMR. M_SEN ; Stack Extension Enable bit in OMR. DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor A-19...

  • Page 302: Interrupt Equates

    I_TIM0C I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C I_VEC+$28 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow I_TIM2C I_VEC+$2C ; TIMER 2 compare DSP56311 User’s Manual, Rev. 2 A-20 Freescale Semiconductor...
  • Page 303 ; EFCOP Interrupts ;------------------------------------------------------------------------ I_FDIBE I_VEC+$68 ; EFCOP Input Buffer Empty I_FDOBF I_VEC+$6A ; EFCOP Output Buffer Full ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor A-21...
  • Page 304 Bootstrap Program DSP56311 User’s Manual, Rev. 2 A-22 Freescale Semiconductor...
  • Page 305 Table B-5, Interrupt Source Priorities Within an IPL, on page B-10 lists the priorities of specific interrupts within interrupt priority levels. The programming sheets appear in this manual as figures (listed in Table B-1); they show the major programmable registers on the DSP56311. Table B-1. Guide to Programming Sheets Module...

  • Page 306: Programming Reference

    $FFF9 $FFFFF9 Address Attribute Register 0 (AAR0) $FFF8 $FFFFF8 Address Attribute Register 1 (AAR1) $FFF7 $FFFFF7 Address Attribute Register 2 (AAR2) $FFF6 $FFFFF6 Address Attribute Register 3 (AAR3) $FFF5 $FFFFF5 ID Register (IDR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 307 DMA Counter (DCO4) $FFDC $FFFFDC DMA Control Register (DCR4) DMA5 $FFDB $FFFFDB DMA Source Address Register (DSR5) $FFDA $FFFFDA DMA Destination Address Register (DDR5) $FFD9 $FFFFD9 DMA Counter (DCO5) $FFD8 $FFFFD8 DMA Control Register (DCR5) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 308 Host Control Register (HCR) $FFC1 $FFFFC1 Reserved $FFC0 $FFFFC0 Reserved Port C $FFBF $FFFFBF Port C Control Register (PCRC) $FFBE $FFFFBE Port C Direction Register (PRRC) $FFBD $FFFFBD Port C GPIO Data Register (PDRC) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 309 ESSI 1 Receive Slot Mask Register B (RSMB1) $FFA0 $FFFFA0 Reserved Port E $FF9F $FFFF9F Port E Control Register (PCRE) $FF9E $FFFF9E Port E Direction Register (PRRE) $FF9D $FFFF9D Port E GPIO Data Register (PDRE) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 310 $FFFF85 Timer 2 Compare Register (TCPR2) $FF84 $FFFF84 Timer 2 Count Register (TCR2) $FF83 $FFFF83 Timer Prescaler Load Register (TPLR) $FF82 $FFFF82 Timer Prescaler Count Register (TPCR) $FF81 $FFFF81 Reserved $FF80 $FFFF80 Reserved DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 311 EFCOP Control Status Register (FCSR) $FFB3 $FFFFB3 EFCOP Filter Count (FCNT) Register $FFB2 $FFFFB2 EFCOP K-Constant Register (FKIR) $FFB1 $FFFFB1 EFCOP Data Output Register (FDOR) $FFB0 $FFFFB0 EFCOP Data Input Register (FDIR) $FFAF– $FFFFAF– Reserved $FF80 $FFFF80 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 312 ESSI0 Receive Last Slot VBA:$36 0–2 ESSI0 Transmit Data VBA:$38 0–2 ESSI0 Transmit Data With Exception Status VBA:$3A 0–2 ESSI0 Transmit Last Slot VBA:$3C 0–2 Reserved VBA:$3E 0–2 Reserved VBA:$40 0–2 ESSI1 Receive Data DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 313 Host Transmit Data Empty VBA:$64 0–2 Host Command (Default) VBA:$66 0–2 Reserved VBA:$68 0–2 EFCOP Data Input Buffer Empty VBA:$6A 0–2 EFCOP Data Output Buffer Full VBA:$6C 0–2 Reserved VBA:$6E 0–2 Reserved VBA:$FE 0–2 Reserved DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor...
  • Page 314 ESSI1 Receive Last Slot Interrupt ESSI1 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line DSP56311 User’s Manual, Rev. 2 B-10 Freescale Semiconductor...

  • Page 315: Interrupt Sources And Priorities

    Interrupt Source SCI Timer Timer0 Overflow Interrupt Timer0 Compare Interrupt Timer1 Overflow Interrupt Timer1 Compare Interrupt Timer2 Overflow Interrupt Timer2 Compare Interrupt EFCOP Data Input Buffer Empty Lowest EFCOP Data Output Buffer Full DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-11...
  • Page 316 15 14 13 12 11 10 9 Extended Mode Register (EMR) Mode Register (MR) Condition Code Register (CCR) Status Register (SR) Read/Write = Reserved, Program as 0 Reset = $C00300 Figure B-1. Status Register (SR) DSP56311 User’s Manual, Rev. 2 B-12 Freescale Semiconductor...

  • Page 317: Programming Sheets

    APD ABE BRT TAS CPD1 CPD0 MC MB = Reserved, Program as 0 Operating Mode Register Reset = $00030X; X = latched from levels on Mode pins Figure B-2. Operating Mode Register (OMR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-13...
  • Page 318 D2L0 D1L1 D1L0 D0L1 D0L0 IDL2 IDL1 IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0 Interrupt Priority Register (IPRC) X:$FFFFFF Read/Write Reset = $000000 Figure B-3. Interrupt Priority Register-Core (IPRC) DSP56311 User’s Manual, Rev. 2 B-14 Freescale Semiconductor...
  • Page 319 15 14 13 12 11 10 9 TOL1 TOL0 SCL1 SCL0 S1L1 S1L0 S0L1 S0L0 HPL1 HPL0 Interrupt Priority Register (IPRP) X:$FFFFFE Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-4. Interrupt Priority Register-Peripherals (IPRP) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-15...
  • Page 320 15 14 13 12 11 10 9 PSTP XTLD XTLR DF2 DF0 MF11 MF10 MF9 MF8 MF5 MF4 MF3 MF2 MF1 MF0 PLL Control Register (PCTL) X:$FFFFFD Read/Write Reset = $000000 Figure B-5. Phase-Lock Loop Control Register (PCTL) DSP56311 User’s Manual, Rev. 2 B-16 Freescale Semiconductor...
  • Page 321 15 14 13 12 11 10 9 BDFW[4–0] BA3W[2–0] BA2W[2–0] BA1W[4–0] BA0W[4–0] X:$FFFFFB Read/Write Bus Control Register (BCR) Reset = $1FFFFF = Reserved, Program as 0 Figure B-6. Bus Control Register (BCR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-17...
  • Page 322 15 14 13 12 11 10 9 BRF[7–0] BSTR BREN BME BPLE BPS[1–0] BRW[1–0] BCW[1–0] DRAM Control Register (DCR) X:$FFFFFA Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-7. DRAM Control Register (DCR) DSP56311 User’s Manual, Rev. 2 B-18 Freescale Semiconductor...
  • Page 323 Address Attribute Registers 2 (AAR2) X:$FFFFF7 Read/Write Address Attribute Registers 1 (AAR1) X:$FFFFF8 Read/Write Address Attribute Registers 0 (AAR0) X:$FFFFF9 Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-8. Address Attribute Registers (AAR[3–0]) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-19...
  • Page 324 15 14 13 12 11 10 9 DTM[2–0] DPR[1–0] DCON DRS[4–0] DAM[5–0] DDS[1–0] DSS[1–0] DMA Control Registers (DCR5–DCR0) X:$FFFFD8, X:$FFFFDC, X:$FFFFE0, Reset = $000000 X:$FFFFE4, X:$FFFFE8, X:$FFFFEC Read/Write Figure B-9. DMA Control Registers 5–0 (DCR[5–0]) DSP56311 User’s Manual, Rev. 2 B-20 Freescale Semiconductor...
  • Page 325 15 14 13 12 11 10 9 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Data Register (HTX) X:$FFFFC7 Write Only Reset = empty Figure B-10. Host Transmit Data Register DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-21...
  • Page 326 HROD HAEN HREN HCSEN HA9EN HA8EN HGEN Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $00 = Reserved, Program as 0 Figure B-11. Host Base Address and Host Port Control Registers DSP56311 User’s Manual, Rev. 2 B-22 Freescale Semiconductor...
  • Page 327 HCP = 1 Host Flag 2 Host Flag 3 HCIE HTIE HRIE X:$FFFFC2 Read /Write Host Control Register (HCR) Reset = $0 = Reserved, Program as 0 Figure B-12. Host Control Register DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-23...
  • Page 328 Handshakes Executing Host Command Interrupts Contains the host command interrupt address Command Vector Register (CVR) Host Address: $1 Read/Write Reset = $32 = Reserved, Program as 0 Figure B-13. Interrupt Control and Command Vector Registers DSP56311 User’s Manual, Rev. 2 B-24 Freescale Semiconductor...
  • Page 329 Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers Host Addresses: $7, $6, $5, $4 Write Only Reset = $00 Figure B-14. Interrupt Vector and Host Transmit Data Registers DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-25...
  • Page 330 DC3 DC2 PM5 PM4 PM3 PM2 PM1 PM0 ESSI Control Register A (CRAx) ESSI0—X:$FFFFB5 Read/Write Reset = $000000 ESSI1—X:$FFFFA5 Read/Write = Reserved, Program as 0 Figure B-15. ESSI Control Register A (CRA) DSP56311 User’s Manual, Rev. 2 B-26 Freescale Semiconductor...
  • Page 331 TE1 TE2 MOD SYN CKP FSP FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0 ESSI Control Register B (CRBx) ESSI0—X:$FFFFB6 Read/Write Reset = $000000 ESSI1—X:$FFFFA6 Read/Write Figure B-16. ESSI Control Register B (CRB) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-27...
  • Page 332 1 = Active Time Slot ESSI Receive Slot Mask B (RSMB[0–1]) ESSI0—X:$FFFFB1 Read/Write Reset = $FFFF ESSI1—X:$FFFFA1 Read/Write = Reserved, Program as 0 Figure B-17. ESSI Transmit and Receive Slot Mask Registers (TSM, RSM) DSP56311 User’s Manual, Rev. 2 B-28 Freescale Semiconductor...
  • Page 333 15 14 13 12 11 10 9 REIE SCKP STIR TMIE ILIE WOMS WAKE SBK SSFTD WDS2 WDS1 WDS0 SCI Control Register (SCR) X:$FFFF9C Read/Write Reset $000000 = Reserved, Program as 0 Figure B-18. SCI Control Register (SCR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-29...
  • Page 334 15 14 13 12 11 10 TCM RCM COD CD11 CD10 CD9 SCI Clock Control Register (SCCR) Address X:$FFFF9B Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-19. SCI Clock Control Registers (SCCR) DSP56311 User’s Manual, Rev. 2 B-30 Freescale Semiconductor...
  • Page 335 15 14 13 12 11 10 9 Prescaler Preload Value (PL [20–0]) Timer Prescaler Load Register (TPLR) X:$FFFF83 Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-20. Timer Prescaler Load Register (TPLR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-31...
  • Page 336 15 14 13 12 11 10 9 TRM INV TCIE TQIE Timer Control/Status Register TCSR0:$FFFF8F Read/Write Reset = $000000 TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write = Reserved, Program as 0 Figure B-21. Timer Control/Status Register (TCSR) DSP56311 User’s Manual, Rev. 2 B-32 Freescale Semiconductor...
  • Page 337 15 14 13 12 11 10 9 Timer Count Value TCR0—X:$FFFF8C Read Only Timer Count Register (TCR[0–2]) TCR1—X:$FFFF88 Read Only Reset = $000000 TCR2—X:$FFFF84 Read Only Figure B-22. Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-33...
  • Page 338 DRx holds value of corresponding HI08 GPIO pin. Function depends on HDDR. Host Data Register (HDR) X:$FFFFC9 Write Reset = Undefined Figure B-23. Host Data Direction and Host Data Registers (HDDR, HDR) DSP56311 User’s Manual, Rev. 2 B-34 Freescale Semiconductor...
  • Page 339 PDn is reflected on port pin n PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 Port C GPIO Data Register (PDRC) X:$FFFFBD Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-24. Port C Registers (PCRC, PRRC, PDRC) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-35...
  • Page 340 PDn is reflected on port pin n PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 Port D GPIO Data Register (PDRD) X:$FFFFAD Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-25. Port D Registers (PCRD, PRRD, PDRD) DSP56311 User’s Manual, Rev. 2 B-36 Freescale Semiconductor...
  • Page 341 PDn is reflected on port pin n PDE2 PDE1 PDE0 Port E GPIO Data Register (PDRE) X:$FFFF9D Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-26. Port E Registers (PCRE, PRRE, PDRE) DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-37...
  • Page 342 FOM1FOM0 FUPD FADP FLT OBF IBE CONT EFCOP Control Status Register (FCSR)Y:$FFFFB4 Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-27. EFCOP Counter and Control Status Registers (FCNT and FCSR) DSP56311 User’s Manual, Rev. 2 B-38 Freescale Semiconductor...
  • Page 343 15 14 13 12 11 10 9 Filter Deci- Filter Channels Value mation Value EFCOP Decimation/Channel Count Register (FDCH) Y:$FFFFB8 Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-28. EFCOP FACR, FDBA, FCBA, and FDCH Registers DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor B-39...
  • Page 344 Programming Reference DSP56311 User’s Manual, Rev. 2 B-40 Freescale Semiconductor...
  • Page 345 DRAM Control Register (DCR) 4-20 JSCLR 5-1 Bus Mastership Enable (BME) bit 4-24 JSET 5-1 Bus Number of Address Bits to Compare (BNC) bits 4-25 JSSET 5-1 Bus Packing Enable (BPAC) bit 4-26 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-1...
  • Page 346 Prescale Modulus Select (PM) 7-15 Decimation/Channel Count Register (FDCH) 10-42 Prescaler Range (PSR) 7-15 Filter Channels (FCHL) 10-42 programming sheet B-26 Filter Decimation (FDCM) 10-42 Select SCK (SSC1) 7-13 Direct Memory Access (DMA) 6-5 DSP56311 User’s Manual, Rev. 2 Index-2 Freescale Semiconductor...
  • Page 347 DSP core Filter Data Output Interrupt Enable (FDOIE) 10-38 programming model 6-11 Filter Enable (FEN) 10-39 DSP56300 Filter Multichannel Mode (FMLC) 10-38 core 1-1 Filter Operation Mode (FOM) 10-39 Family Manual 1-1 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-3...
  • Page 348 Port Control Register D (PCRD) 7-34 Frame Sync Relative Timing (FSR) 7-21 Port Data Register (PDR) 7-35 Mode Select (MOD) 7-20 Port Data Register C (PDRC) 7-35 programming sheet B-27 Port Data Register D (PDRD) 7-35 DSP56311 User’s Manual, Rev. 2 Index-4 Freescale Semiconductor...
  • Page 349 7-11 Filter Count Register (FCNT) 10-36 word length frame sync timing 7-11 Filter Data Base Address (FDBA) register 10-41 EOM byte 4-10 Filter Data Input Buffer Empty (FDIBE) bit 10-37 equalization 10-1 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-5...
  • Page 350 Global Data Bus (GDB) 1-10 programming sheet B-24 GPIO 2-2 configuring host request mode 6-8 Timers 2-2 control operating mode 6-16 Ground 2-4 core communication with HI08 registers 6-11 PLL 2-4 core interrupts host command 6-7 DSP56311 User’s Manual, Rev. 2 Index-6 Freescale Semiconductor...
  • Page 351 Host Flags 2, 3 (HF) 6-12 handshaking protocols 6-1 Host Receive Interrupt Enable (HRIE) 6-13 instructions 6-1 Host Transmit Interrupt Enable (HTIE) 6-13 mapping 6-1 programming sheet B-23 HREQ/HTRQ handshake flags 6-22 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-7...
  • Page 352 Host Multiplexed Bus (HMUX) bit 6-17 X data Memory 3-5 Host Port Control Register (HPCR) 6-3 6-12 6-16 6-20 Y data Memory 3-7 6-21 6-29 6-30 Idle Line Flag (IDLE) bit 8-16 Host Acknowledge Enable (HAEN) 6-18 DSP56311 User’s Manual, Rev. 2 Index-8 Freescale Semiconductor...
  • Page 353 10-1 ESSI0 Interrupt Priority Level (S0L) 4-15 MODD, MODC, MODB, and MODA 8-7 ESSI1 Interrupt Priority Level (S1L) 4-15 mode control 2-8 HI08 Interrupt Priority Level (HPL) 4-15 Mode Register (MR) 4-5 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-9...
  • Page 354 Stack Extension Wrap Flag (WRP) 4-11 ESSI1 5-7 Stack Extension XY Select (XYS) 4-11 Port D Control Register (PCRD) 7-34 Stop Delay Mode (SD) 4-13 programming sheet B-36 TA Synchronize Select (TAS) 4-12 DSP56311 User’s Manual, Rev. 2 Index-10 Freescale Semiconductor...
  • Page 355 Transmit Clock Source (TCM) 8-17 program 3-1 SCI Clock Polarity (SCKP) bit 8-11 reading status registers 5-2 SCI Control Register (SCR) 8-8 8-10 Receive Byte Registers (RXH, RXM, RXL) 6-5 6-27 bit definitions 8-11 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-11...
  • Page 356 SCI receive data with exception Framing Error Flag (FE) 8-15 interrupt 8-11 Idle Line Flag (IDLE) 8-16 exceptions 8-8 Overrun Error Flag (OR) 8-16 Idle Line 8-8 Parity Error (PE) 8-15 DSP56311 User’s Manual, Rev. 2 Index-12 Freescale Semiconductor...
  • Page 357 Stack Pointer (SP) 1-8 after Reset 9-3 standby mode enabling 9-4 Stop 1-6 exception 9-4 Wait 1-6 Compare 9-4 Status Register (SR) 1-8 Overflow 9-4 bit definitions 4-6 GPIO 5-8 Condition Code Register (CCR) 4-5 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-13...
  • Page 358 Data Output (DO) 9-25 7-31 Direction (DIR) 9-25 Transmitter Empty (TRNE) bit 8-16 Inverter (INV) 9-25 9-27 Transmitter Enable (TE) bit 8-12 Prescaler Clock Enable (PCE) 9-24 Transmitter Ready (TRDY) bit 6-26 DSP56311 User’s Manual, Rev. 2 Index-14 Freescale Semiconductor...
  • Page 359 Y data Memory 3-5 internal 3-5 Y data memory 1-6 Y I/O space 3-7 Y Memory Address Bus (YAB) 1-11 Y Memory Data Bus (YDB) 1-11 Y Memory Expansion Bus 1-10 Zero (Z) bit 4-10 DSP56311 User’s Manual, Rev. 2 Freescale Semiconductor Index-15...
  • Page 360 Index DSP56311 User’s Manual, Rev. 2 Index-16 Freescale Semiconductor...

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