Serial Receive Data Signal (Srd); Serial Clock (Sck); Serial Control Signal (Sc0) - Freescale Semiconductor DSP56311 User Manual

transmitted, the signal does not assume a high-impedance state. The
STD
programmed as a GPIO signal (

7.2.2 Serial Receive Data Signal (SRD)

receives serial data and transfers the data to the receive shift register.
SRD
programmed as a GPIO signal (

7.2.3 Serial Clock (SCK)

is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The signal is
SCK
a clock input or output used by all the enabled transmitters and receivers in Synchronous modes
or by all the enabled transmitters in Asynchronous modes. See Table 7-1 for details.
programmed as a GPIO signal (
SYN SCKD
0 0
0 0
0 1
0 1
1 0
1 1
Note: Although an external serial clock can be independent of and asynchronous to the DSP
system clock, the external ESSI clock frequency must not exceed F
ESSI phase must exceed the minimum of 1.5
ESSI clock frequency must not exceed F

7.2.4 Serial Control Signal (SC0)

ESSI0: SC00; ESSI1: SC10
To determine the function of the
according to Table 7-2. In Asynchronous mode, this signal is used for the receive clock I/O. In
Synchronous mode, this signal is the transmitter data out signal for transmit shift register TX1 or
for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for
addressing in codec systems.
If is configured as a serial flag signal or receive clock signal, its direction is determined by
SC0
the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as
an output, functions as the serial Output Flag 0 (OF0) or as a receive shift register clock
SC0
Freescale Semiconductor
) when the ESSI
P5
) when the
P4
) when not used as the ESSI clock.
P3
Table 7-1. ESSI Clock Sources
SCD0 RX Clock Source
Asynchronous
0 EXT, SC0
1 INT
0 EXT, SC0
1 INT
Synchronous
0/1 EXT, SCK
0/1 INT
signal, select either Synchronous or Asynchronous mode,
SC0
DSP56311 User's Manual, Rev. 2
function is not in use.
STD
function is not in use.
SRD
RX Clock
TX Clock Source
Out
— EXT, SCK
SC0 EXT, SCK
—
SC0
— EXT, SCK
SCK
cycles. The internally sourced
CLKOUT
/4.
core
ESSI Data and Control Signals
signal can be
STD
can be
SRD
SCK
TX Clock Out
—
—
INT SCK
INT SCK
—
INT SCK
/3, and each
core
can be
7-3