Interrupt And Mode Control - Freescale Semiconductor DSP56311 User Manual

Signals/Connections
Signal State During Reset,
Type
Name
BCLK Output Tri-stated
BCLK Output Tri-stated

2.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip's operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Signal Name Type
RESET Input
MODA Input
IRQA Input
MODB Input
IRQB Input
2-8
Table 2-8. External Bus Control Signals (Continued)
Stop, or Wait
Bus Clock
When the DSP is the bus master, BCLK is active when the OMR[ATE] is set.
When BCLK is active and synchronized to CLKOUT by the internal PLL,
BCLK precedes CLKOUT by one-fourth of a clock cycle.
Note: At operating frequencies above 100 MHz, this signal produces a
low-amplitude waveform that is not usable externally by other devices.
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal.
Otherwise, the signal is tri-stated.
Note: At operating frequencies above 100 MHz, this signal produces a
low-amplitude waveform that is not usable externally by other devices.
Table 2-9. Interrupt and Mode Control
State During
Reset
Input, Reset—When asserted, places the chip in the Reset state and
Schmitt-trigger resets the internal phase generator. The Schmitt-trigger input allows
a slowly rising input (such as a capacitor charging) to reset the chip
reliably. When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC, and
MODD inputs. The RESET signal must be asserted after power-up.
Input, Mode Select A—MODA, MODB, MODC, and MODD select one of
Schmitt-trigger 16 initial chip operating modes, latched into the OMR when the
RESET signal is deasserted.
External Interrupt Request A—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the processor
is in the STOP or WAIT standby state and IRQA is asserted, the
processor exits the STOP or WAIT state.
Input, Mode Select B—MODA, MODB, MODC, and MODD select one of
Schmitt-trigger 16 initial chip operating modes, latched into the OMR when the
RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the processor
is in the WAIT standby state and IRQB is asserted, the processor
exits the WAIT state.
DSP56311 User's Manual, Rev. 2
Signal Description
Signal Description
Freescale Semiconductor