Operation; Timer After Reset; Timer Initialization - Freescale Semiconductor DSP56311 User Manual

GDB
Control/Status
Register
Timer Control
TIO CLK/2

9.2 Operation

This section discusses the following timer basics:
Reset
Initialization
Exceptions

9.2.1 Timer After Reset

A hardware signal or software reset instruction clears the Timer Control and Status
RESET
Register for each timer, thus configuring each timer as a GPIO. A timer is active only if the timer
enable bit 0 (TCSR[TE]) in the specific timer TCSR is set.

9.2.2 Timer Initialization

To initialize a timer, do the following:
Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE]
1.
bit.
Configure the control register (TCSR) to set the timer operating mode. Set the interrupt
2.
enable bits as needed for the application.
Freescale Semiconductor
24
24
TCSR
Load
Register
9
2
Logic
Prescaler CLK
Figure 9-2. Timer Module Block Diagram
DSP56311 User's Manual, Rev. 2
24 24
TCR
TLR
Count
Register
24 24
24
Counter
Timer interrupt/DMA request
Operation
24
TCPR
Compare
Register
24
=
9-3