Essi Control Register A (Cra) - Freescale Semiconductor DSP56311 User Manual

This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals and
Registers, on page 7-34 covers ESSI GPIO.

7.5.1 ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct
the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word
length, and number of words per frame for serial data.
23 22 21
SSC1 WL2
11 10 9
PSR
—Reserved bit; read as 0; write to 0 for future compatibility.
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
Bit Number Bit Name
23
22 SSC1
Freescale Semiconductor
20 19 18
WL1 WL0 ALC
8 7 6
PM7 PM6
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
Figure 7-2. ESSI Control Register A(CRA)
Reset Value
0 Reserved. Write to 0 for future compatibility.
0 Select SC1
Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal is configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is
configured as output (SCD1 = 1).
DSP56311 User's Manual, Rev. 2
17 16 15
DC4 DC3
5 4 3
PM5 PM4 PM3
Description
ESSI Programming Model
14 13 12
DC2 DC1 DC0
2 1 0
PM2 PM1 PM0
7-13