Filter Multiplier And Accumulator (Fmac) - Freescale Semiconductor DSP56311 User Manual

Architecture Overview
The EFCOP connects to the shared memory in place of the DMA bus. Simultaneous core and
EFCOP accesses to the same memory module block (1024 locations) of shared memory are not
permitted. It is your responsibility to prevent such simultaneous accesses. Figure 10-3 illustrates
the memory shared between the core and the EFCOP.
X RAM
Y RAM
Data X RAM Y RAM P RAM
Coefficients
(FDM) (FCM)
YDB
PDB
XDB
CDB
FDB
DDB
CORE
EFCOP
GDB
Figure 10-3. EFCOP Memory Organization
.

10.2.3 Filter Multiplier and Accumulator (FMAC)

The FMAC machine can perform a 24-bit × 24-bit multiplication with accumulation in a 56-bit
accumulator. The FMAC operates a pipeline: the multiplication is performed in one clock cycle,
and the accumulation occurs in the following clock cycle. Throughput is one MAC result per
clock cycle. The two MAC operands are read from the FDM and from the FCM. The full 56-bit
width of the accumulator is used for intermediate results during the filter calculations.
For operations with saturation mode disabled, the final result is rounded according to the selected
rounding mode and limited to the most positive number ($7FFFFF, if overflow occurred) or most
negative number ($800000, if underflow occurred) after processing of all filter taps is completed.
In saturation mode, the result is limited to the most positive number ($7FFFFF, if overflow
occurred), or the most negative number ($800000, if underflow occurred) after each MAC
operation. The 24-bit result from the FMAC is stored in the EFCOP output buffer, FDOR.
Operating in sixteen-bit arithmetic mode, the FMAC performs a 16-bit × 16-bit multiplication
with accumulation into a 40-bit accumulator. As with 24-bit operations, if saturation mode is
disabled, the result is rounded according to the selected rounding mode and limited to the most
positive number ($7FFF, if overflow occurred) or the most negative number ($8000, if underflow
occurred) after processing of all filter taps is completed. In saturation mode, the result is limited
to the most positive number ($7FFF, if overflow occurred) or the most negative number ($8000,
DSP56311 Reference Manual, Rev. 2
Freescale Semiconductor 10-5