Endian Modes - Freescale Semiconductor DSP56311 User Manual

respectively. When host requests are enabled, the host request pins operate as shown in Figure
6-3.
7
$2
HREQ 0
Host Request
Asserted
7
$0 INIT 0
Table 6-5 shows the operation of the
test these ICR bits to determine the interrupt source.
Table 6-5. HREQ Pin Operation In Single Request Mode (ICR[2] = HDRQ = 0)
ICR[1] = TREQ
0
0
1
1
Table 6-6 shows the operation of the transmit request (
with dual host requests enabled.
Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2] = HDRQ = 1)
ICR[1] = TREQ ICR[0] = RREQ
0
0
1
1

6.4.5 Endian Modes

The Host Little Endian bit in the host-side Interface Control Register (ICR[5] = HLEND) allows
the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian
mode (HLEND = 1), a host transfer occurs as shown in Figure 6-4.
Freescale Semiconductor
0 HF3 HF2 TRDY
0 HF1 HF0 HLEND TREQ RREQ ICR
Figure 6-3. HI08 Host Request Structure
HREQ
ICR[0] = RREQ
0
1
0
1
0 No interrupts
1 No interrupts
0 TXDE Request enabled
1 TXDE Request enabled
DSP56311 User's Manual, Rev. 2
Status
0
TXDE RXDF ISR
0
Enable
pin when a single request line is used. The host can
No interrupts
RXDF request enabled
TXDE request enabled
RXDF and TXDE request enabled
) and receive request (
HTRQ
HTRQ Pin
Host Request
Signals
HRRQ
HREQ
HTRQ
HREQ Pin
HRRQ
HRRQ Pin
No interrupts
RXDF request enabled
No interrupts
RXDF request enabled
Operation
) lines
6-9