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Host Interface (HI08)
Host processors can use standard host processor instructions (for example, byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are aligned so that
8-bit host processors can use 8-, 16-, or 24-bit load and store instructions for data transfers. The
HREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled or interrupt-driven
data transfers with the host processor. Because of the speed of the DSP56311 interrupt response,
most host microprocessors can load or store data at their maximum programmed I/O instruction
rate without testing the handshake flags for each transfer. If full handshake is not needed, the host
processor can treat the DSP56311 as a fast device, and data can be transferred between the host
processor and the DSP56311 at the fastest data rate of the host processor.
One of the most innovative features of the host interface is the host command feature. With this
feature, the host processor can issue vectored interrupt requests to the DSP56311. The host can
select any of 128 DSP interrupt routines for execution by writing a vector address register in the
HI08. This flexibility allows the host processor to execute up to 128 pre-programmed functions
inside the DSP56311. For example, the DSP56311 host interrupts allow the host processor to
read or write DSP registers (X, Y, or program memory locations), force interrupt handlers (for
example, ESSI, SCI,
operations.
Note:
When the DSP enters Stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the HI08
configuration remains unchanged in Stop mode, the core cannot be restarted via the
HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless you
provide some other mechanism to exit stop mode.
Host Address
0
1
2
3
4
5
6
7
6.7.1 Interface Control Register (ICR)
The ICR is an 8-bit read/write control register by which the host processor controls the HI08
interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write register, which
allows the use of bit manipulation instructions on control register bits. Hardware and software
reset clear the ICR bits.
6-22
,
interrupt routines), and perform control or debugging
IRQA
IRQB
Table 6-14. Host-Side Register Map
Big Endian HLEND = 0
ICR
CVR
ISR
IVR
00000000
RXH/TXH
RXM/TXM
RXL/TXL
DSP56311 User's Manual, Rev. 2
Little Endian HLEND = 1
ICR
CVR
ISR
IVR
00000000
RXL/TXL
RXM/TXM
RXH/TXH
Register Name
Interface Control
Command Vector
Interface Status
Interrupt Vector
Unused
Receive/Transmit
Data
Freescale Semiconductor
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