Efcop Alu Control Register (Facr) - Freescale Semiconductor DSP56311 User Manual

Enhanced Filter Coprocessor

10.4.6 EFCOP ALU Control Register (FACR)

The FACR is a read/write register by which the DSP56300 core controls the main operation
modes of the EFCOP ALU.
23 22 21
11 10 9
= Reserved bit; read as 0; write with 0 for future compatibility
Reserved for internal use; read as 0; write with 0 for proper use.
=
Table 10-8. EFCOP ALU Control Register (FACR) Bits
Bit
Bit Name
Number
23–16
15–12
11–7
6 FISL
5 FSA
4 FSM
3–2 FRM[1–0]
10-40
20 19
8 7
Reset
Value
0 Reserved. They read as 0; write with 0 for future compatibility.
0 Reserved for internal use. Written as 0 for proper operation.
0 Reserved and unused. They read as 0; write with 0 for future compatibility.
0 Filter Input Scale
When set, this read/write control bit directs the EFCOP ALU to scale the IIR feedback
terms but not the IIR input. When cleared, the EFCOP ALU scales both the IIR feedback
terms and the IIR input. The scaling value in both cases is determined by the FSCL[1:0]
bits.
0 Filter Sixteen-bit Arithmetic (FSA) Mode
When set, this read/write control bit enables FSA mode. In this mode, the rounding of
the arithmetic operation is performed on Bit 31 of the 56-accumulator instead of the
usual bit 23 of the 56-bit accumulator. The scaling of the EFCOP data ALU is affected
accordingly.
0 Filter Saturation Mode
When set, this read/write control bit selects automatic saturation on 48 bits for the
results going to the accumulator. A special circuit inside the EFCOP MAC unit then
saturates those results. The purpose of this bit is to provide arithmetic saturation mode
for algorithms that do not recognize or cannot take advantage of the extension
accumulator.
0 Filter Rounding Mode
These read/write control bits select the type of rounding performed by the EFCOP data
ALU during arithmetic operation:
• FRM = 00—Convergent rounding
• FRM = 01—Two's complement rounding
• FRM = 10—Truncation (no rounding)
• FRM = 11—Reserved for future expansion
These bits affect operation of the EFCOP data ALU.
DSP56311 Reference Manual, Rev. 2
18 17 16
6 5 4
FISL FSA FSM
Description
15 14 13
3 2 1
FRM1 FRM0 FSCL1
Freescale Semiconductor
12
0
FSCL0