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Host Interface (HI08)
6.6.7 Host Transmit (HTX) Register
The HTX register is used in DSP-to-host data transfers. The DSP56311 views it as a 24-bit
write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the host transfer
data empty bit (HSR[HTDE]) on the DSP side. The contents of the HTX register are transferred
as 24-bit data to the Receive Data Registers (RXH:RXM:RXL) when both HSR[HTDE] and
receive data full (ISR[RXDF]) on the host-side bits are cleared. This transfer operation sets the
ISR[RXDF] and HSR[HTDE] bits. The DSP56311 can set the HCR[HTIE] bit to cause a host
transmit data interrupt when HSR[HTDE] is set. To prevent the previous data from being
overwritten, the DSP56311 should never write to the HTX when HSR[HTDE] is cleared.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of the status bits
within the next two cycles, the bit does not reflect its current status. For details, see
Section 6.4.1, Software Polling, on page 6-6.
6.6.8 Host Receive (HRX) Register
The HRX register is used in host-to-DSP data transfers. The DSP56311 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the transmit data
registers (TXH:TXM:TXL on the host side) when both the transmit data register empty
(ISR[TXDE]) on the host side and host receive data full (HSR[HRDF]) on the DSP side are
cleared. The transfer operation sets both ISR[TXDE] and HSR[HRDF]. When the HSR[HRDF]
is set, the HRX register contains valid data. The DSP56311 can set the HCR[HRIE] to cause a
host receive data interrupt when HSR[HRDF] is set. When the DSP56311 reads the HRX
register, the HSR[HRDF] bit is cleared.
Note:
The DSP56311 should never try to read the HRX register if the HSR[HRDF] bit is
already cleared.
6.6.9 DSP-Side Registers After Reset
Table 6-13 shows the results of the four reset types on the bits in each of the HI08 registers
accessible to the DSP56311. The hardware reset (HW) is caused by the
software reset (SW) is caused by execution of the RESET instruction. The individual reset (IR)
occurs when HPCR[HEN] is cleared. The stop reset (ST) occurs when the STOP instruction
executes.
6-20
DSP56311 User's Manual, Rev. 2
signal. The
RESET
Freescale Semiconductor
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