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1.1 Power
Power Name
V
PLL Power—V
CCP
an extremely low impedance path to the V
V
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from
CCQL
all other chip power inputs.
V
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip
CCQH
power inputs , except V
V
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
CCA
to all other chip power inputs, except V
V
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
CCD
other chip power inputs, except V
V
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
CCC
chip power inputs, except V
V
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
CCH
inputs, except V
V
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
CCS
externally to all other chip power inputs, except V
Note: The user must provide adequate external decoupling capacitors for all power connections.
1.2 Ground
Name
GND
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
P
path to ground. V
package.
GND
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
P1
path to ground.
GND
Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
1.3 Clock
Signal Name
Type
EXTAL
Input
XTAL
Output
Freescale Semiconductor
Table 1-2.
dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
CC
power rail.
CC
.
CCQL
.
CCQL
.
CCQL
.
CCQL
.
CCQL
Table 1-3.
should be bypassed to GND
CCP
Table 1-4.
State During
Reset
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
DSP56311 Technical Data, Rev. 8
Power Inputs
Description
.
CCQL
Grounds
Description
by a 0.47 µF capacitor located as close as possible to the chip
P
Clock Signals
Signal Description
Power
1-3
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