Table of Contents
Advertisement
Core Configuration
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
3
N
2
Z
1
V
0
C
4.3.2
Operating Mode Register (OMR)
The OMR is a read/write register divided into three byte-sized units. The lowest two bytes (EOM
and COM) control the chip's operating mode. The high byte (SCS) controls and monitors the
stack extension. The OMR control bits are shown in Figure 4-2.
Stack Control/Status (SCS)
23
22
21
20
19
MSW[1–0] SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] MS
Reset:
0
0
0
0
0
After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA,
*
respectively).
Reserved bit. Read as zero; write to zero for future compatibility
The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected only
by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI, and
other instructions, such as MOVEC, that specify OMR as a destination). The Stack
Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and
RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode bits
(MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC,
MODB, and MODA respectively. Table 4-3 defines the DSP56311 OMR bits.
4-10
Reset Value
0
Negative
Set if the MSB of the result is set; otherwise, this bit is cleared.
0
Zero
Set if the result equals zero; otherwise, this bit is cleared.
0
Overflow
Set if an arithmetic overflow occurs in the 56-bit result; otherwise, this bit is
cleared. V indicates that the result cannot be represented in the
accumulator register (that is, the register overflowed). In Arithmetic
Saturation mode, an arithmetic overflow occurs if the Data ALU result is not
representable in the accumulator without the extension part (that is, 48-bit
accumulator or the 32-bit accumulator in Arithmetic Sixteen-bit mode).
0
Carry
Set if a carry is generated by the MSB resulting from an addition operation.
This bit is also set if a borrow is generated in a subtraction operation;
otherwise, this bit is cleared. The carry or borrow is generated from Bit 55 of
the result. The C bit is also affected by bit manipulation, rotate, and shift
instructions.
Extended Operating Mode (EOM)
18
17
16
15
14
13
0
0
0
0
0
0
Figure 4-2. Operating Mode Register (OMR)
DSP56311 User's Manual, Rev. 2
Description
12
11
10
9
8
7
0
0
0
1
1
0
Chip Operating Mode (COM)
6
5
4
3
2
1
SD
EBD MD MC MB MA
0
0
0
*
*
*
Freescale Semiconductor
0
*
Advertisement
Table of Contents
