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Enhanced Filter Coprocessor
Table 10-1. EFCOP Registers Accessible Through the PMB (Continued)
Register Name
EFCOP ALU Control
Register (FACR)
EFCOP Data Buffer Base
Address (FDBA)
EFCOP Coefficient Buffer
Base Address (FCBA)
Decimation/
Channel Count Register
(FDCH)
10.2.2 EFCOP Memory Banks
The EFCOP contains two memory banks:
Filter Data Memory (FDM). This 24-bit-wide memory bank is mapped as X memory and
stores input data samples for EFCOP filter processing. The FDM is written via a 4-word
FIFO (FDIR), and its addressing is generated by the EFCOP address generation logic. The
input data samples are read sequentially from the FDM into the MAC. The FDM is
accessible for writes by the core, and the DMA controller and is shared with the 12 K
lowest locations ($0–$2FFF) of the on-chip internal X memory.
Filter Coefficient Memory (FCM). This 24-bit-wide memory bank is mapped as Y
memory and stores filter coefficients for EFCOP filter processing. The FCM is written via
the DSP56300 core, and the EFCOP address generation logic generates its addressing. The
filter coefficients are read sequentially from the FCM into the MAC. The FCM is
accessible for writes only by the core. The FCM is shared with the 12 K lowest locations
($0–$2FFF) of the on-chip internal Y memory.
Note:
The filter coefficients, H(n), are stored in "reverse order," where H(N – 1) is stored at
the lowest address of the FCM register as shown in Figure 10-2.
Data
Memory
Bank
(FDM)
10-4
A 24-bit read/write register used by the DSP56300 core to program the EFCOP data ALU
operating modes.
A 16-bit read/write register used by the DSP56300 core to indicate the EFCOP the data buffer
base start address pointer in FDM RAM.
A 16-bit read/write register by which the DSP56300 core indicates the EFCOP coefficient buffer
base start address pointer in FCM RAM.
A 24-bit register that sets the number of channels in multichannel mode and the filter
decimation ratio. The EFCOP address generation logic uses this information to supply the
correct addressing to the FDM and FCM.
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
-
-
Figure 10-2. Storage of Filter Coefficients
DSP56311 Reference Manual, Rev. 2
Description
H(N - 1)
H(N - 2)
-
-
Coefficient
Memory
-
Bank
-
(FCM)
H(1)
H(0)
Freescale Semiconductor
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