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2.1 Power
Power Name
V
PLL Power—V
CCP
should be provided with an extremely low impedance path to the V
V
Quiet Core (Low) Power—An isolated power for the DSP56300 core processing logic. This
CCQL
input must be isolated externally from all other chip power inputs. The user must provide
adequate external decoupling capacitors.
V
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied
CCQH
externally to all other chip power inputs, except V
decoupling capacitors.
V
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input
CCA
must be tied externally to all other chip power inputs, except V
adequate external decoupling capacitors.
V
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be
CCD
tied externally to all other chip power inputs, except V
external decoupling capacitors.
V
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied
CCC
externally to all other chip power inputs, except V
decoupling capacitors.
V
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all
CCH
other chip power inputs, except V
capacitors.
V
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This
CCS
input must be tied externally to all other chip power inputs, except V
adequate external decoupling capacitors.
Freescale Semiconductor
Table 2-2. Power Inputs
Description
dedicated for PLL use. The voltage should be well-regulated and the input
CC
. The user must provide adequate external decoupling
CCQL
DSP56311 User's Manual, Rev. 2
power rail.
CC
. The user must provide adequate
CCQL
. The user must provide
CCQL
. The user must provide adequate
CCQL
. The user must provide adequate external
CCQL
. The user must provide
CCQL
Power
2-3
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