Measurement Input Width (Mode 4) - Freescale Semiconductor DSP56311 User Manual

Triple Timer Module

9.3.2.1 Measurement Input Width (Mode 4)

Bit Settings
TC3 TC2 TC1
0 1 0
In Mode 4, the timer counts the number of clocks that occur between opposite edges of an input
signal. After the first appropriate transition (as determined by the TCSR[INV] bit) occurs on the
input signal, the counter is loaded with the TLR value. If TCSR[INV] is set, the timer starts
TIO
on the first high-to-low (1 to 0) signal transition on the
timer starts on the first low-to-high (that is, 0 to 1) transition on the
transition opposite in polarity to the INV bit setting occurs on the
TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is set. The value of
the counter (which measures the width of the TIO pulse) is loaded into the TCR, which can be
read to determine the external signal pulse width. If the TCSR[TRM] bit is set, the counter is
loaded with the TLR value on the first timer clock received following the next valid transition on
the input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to
TIO
increment on each timer clock. This process repeats until the timer is disabled.
Mode 4 (internal clock): TRM = 1
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
TCR
TIO pin
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
Figure 9-11. Pulse Width Measurement Mode, TRM = 1
9-12
TC0 Mode
0 4 Input width
first event
N
0 N
width being measured
DSP56311 User's Manual, Rev. 2
Mode Characteristics
Name Function
Measurement
signal. If the INV bit is cleared, the
TIO
TIO
TIO
N + 1
M
TIO Clock
Input Internal
signal. When the first
signal, the counter stops.
M
N + 1
Next 0-to-1 edge
on TIO loads
counter and
process repeats
Interrupt Service
reads TCR; width
= M - N clock
periods
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