Timer Exceptions - Freescale Semiconductor DSP56311 User Manual

24-bit digital signal processor (dsp)
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Triple Timer Module
Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register
3.
(TLR), and Timer Compare Register (TCPR) as needed for the application.
Enable the timer by setting the TCSR[TE] bit.
4.

9.2.3 Timer Exceptions

Each timer can generate two different exceptions:
Timer Overflow (highest priority) — Occurs when the timer counter reaches the overflow
value. This exception sets the TOF bit. TOF is cleared when a value of one is written to it
or when the timer overflow exception is serviced.
Timer Compare (lowest priority) — Occurs when the timer counter reaches the value
given in the Timer Compare Register (TCPR) for all modes except measurement modes.
In measurement modes 4–6, a compare exception occurs when the appropriate transition
occurs on the
TIO
value of one is written to it or when the timer compare interrupt is serviced.
To configure a timer exception, perform the following steps. The example at the right of each
step shows the register settings for configuring a Timer 0 compare interrupt. The order of the
steps is optional except that the timer should not be enabled (step 2e) until all other exception
configuration is complete:
1.
Configure the interrupt service routine (ISR):
a.
Load vector base address register
b.
Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c.
Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt).
Configure the interrupt trigger:
2.
a.
Enable and prioritize overall peripheral interrupt functionality.
b.
Enable a specific peripheral interrupt.
c.
Unmask interrupts at the global level.
d.
Configure a peripheral interrupt-generating function.
e.
Enable peripheral and associated signals.
9-4
signal. The Compare exception sets the TCF bit. TCF is cleared when a
DSP56311 User's Manual, Rev. 2
VBA (b23–8)
p:TIM0C
IPRP (TOL[1–0])
TCSR0 (TCIE)
SR (I[1–0])
TCSR0 (TC[7–4])
TCSR0 (TE)
Freescale Semiconductor

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