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Freescale Semiconductor DSP56311 Technical Data Manual

24-bit digital signal processor
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Freescale Semiconductor
Technical Data
DSP56311
24-Bit Digital Signal Processor
3
16
Triple
SCI
HI08
Timer
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
Program
Clock
PLL
Interrupt
Generator
Controller
EXTAL
XTAL
PCAP
RESET
PINIT/NMI
The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)
controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining
up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
© Freescale Semiconductor, Inc., 1999, 2005. All rights reserved.
6
6
Program
RAM
32 K × 24 bits
ESSI
EFCOP
or
31 K × 24 bits
and
Instruction
Cache
1024 × 24 bits
Peripheral
Expansion Area
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Program
Program
24 × 24 + 56 → 56-bit MAC
Decode
Address
Two 56-bit Accumulators
Controller
Generator
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1. DSP56311 Block Diagram
Memory Expansion Area
X Data
Y Data
RAM
RAM
48 K × 24 bits
48 K × 24 bits
External
Address
Bus
Address
Switch
External
Bus
Interface
and
I - Cache
Control
Control
External
Data
Bus
Switch
Power
Management
Data ALU
JTAG
OnCE™
56-bit Barrel Shifter
DSP56311
Rev. 8, 2/2005
The DSP56311 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
18
applications, correlation, and
general-purpose convolution-
13
based algorithms.
24
What's New?
Rev. 8 includes the following
Data
changes:
• Adds lead-free packaging and
part numbers.
5
DE

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Summary of Contents for Freescale Semiconductor DSP56311

  • Page 1 (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power.

  • Page 2: Table Of Contents

    Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage True Asserted False Deasserted True Asserted False Deasserted Note: Values for , and are defined by individual product specifications. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 3: Features

    Features Table 1 lists the features of the DSP56311 device. Table 1. DSP56311 Features Feature Description • Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O •...

  • Page 4: Target Applications

    IP telephony Product Documentation The documents listed in Table 2 are required for a complete description of the DSP56311 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website.

  • Page 5: Signals/Connections

    Signals/Connections The DSP56311 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1.
  • Page 6 (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively. TIO[0–2] can be configured as GPIO signals. CLKOUT, BCLK, BCLK, CAS, and RAS[0–3] are valid only for operating frequencies ≤ 100 MHz. Figure 1-1. Signals Identified by Functional Group DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 7: Power

    External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 8: External Memory Expansion Port (Port A)

    Schmitt-trigger input is the negative-edge-triggered NMI request internally synchronized to CLKOUT. 1.5 External Memory Expansion Port (Port A) Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri- states the relevant Port A signals: –...

  • Page 9: External Data Bus

    Transfer Acknowledge—If the DSP56311 is the bus master and there is no external bus activity, or the DSP56311 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely.
  • Page 10 (deasserted) when the DSP no longer needs the bus. BR may be asserted or deasserted independently of whether the DSP56311 is a bus master or a bus slave. Bus State during Stop/Wait “parking” allows BR to be deasserted even though the DSP56311 is the bus master.

  • Page 11: Interrupt And Mode Control

    When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after powerup. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 12: Host Interface (Hi08)

    Input or Output Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 13 Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control PB11 Input or Output Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 14 • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. The Wait processing state does not affect the signal state. DSP56311 Technical Data, Rev. 8 1-10...

  • Page 15: Enhanced Synchronous Serial Interface 0 (Essi0)

    Input or Output configured as PC4, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SRD0 through the Port C Control Register. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 1-11...

  • Page 16: Enhanced Synchronous Serial Interface 1 (Essi1)

    Input or Output configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register. DSP56311 Technical Data, Rev. 8 1-12 Freescale Semiconductor...

  • Page 17: Serial Communication Interface (Sci)

    Input or Output configured as PE1, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal TXD through the Port E Control Register. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 1-13...

  • Page 18: Timers

    The Wait processing state does not affect the signal state. 1.11 Timers The DSP56311 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56311 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events.

  • Page 19: Jtag And Once Interface

    JTAG and OnCE Interface 1.12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56311 support circuit-board test strategies based on the IEEE® Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG.
  • Page 20 Signals/Connections DSP56311 Technical Data, Rev. 8 1-16 Freescale Semiconductor...

  • Page 21: Chapter 2 Specifications

    Specifications The DSP56311 is fabricated in high-density CMOS with transistor-transistor logic (TTL) compatible inputs and outputs. 2.1 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings.

  • Page 22: Thermal Characteristics

    Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 23: Dc Electrical Characteristics

    (DC current). To minimize power consumption, the minimum V should be no lower than 0.9 × V should be no higher than 0.1 × V and the maximum V CCQH CCQH DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 24: Ac Electrical Characteristics

    Table 2-2. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal’s transition. DSP56311 output levels are measured with the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.
  • Page 25 2.4.2 External Clock Operation The DSP56311 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1...
  • Page 26 830 × MF 1470 × MF • @ MF > 4 Note: is the value of the PLL capacitor (connected between the PCAP pin and V ) computed using the appropriate expression PCAP listed above. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 27 0.5) × T not enabled (Operating Mode Register Bit 6 = 1) (8.25 ± 0.5) × T • PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop 51.7 58.3 Delay) DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 28 = 1.8 V ± 0.1 V; T = –40°C to +100°C, C = 50 pF. CCQH WS = number of wait states (measured in clock cycles, number of T Use expression to compute maximum value. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 29 Figure 2-3. Reset Timing First Interrupt Instruction A[0–17] Execution/Fetch IRQA, IRQB, IRQC, IRQD, a) First Interrupt Instruction Execution General Purpose IRQA, IRQB, IRQC, IRQD, b) General-Purpose I/O Figure 2-4. External Fast Interrupt Timing DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 30 Operating Mode Select Timing IRQA First Instruction Fetch A[0–17] Figure 2-7. Recovery from Stop State Using IRQA IRQA First IRQA Interrupt A[0–17] Instruction Fetch Figure 2-8. Recovery from Stop State Using IRQA Interrupt Service DSP56311 Technical Data, Rev. 8 2-10 Freescale Semiconductor...
  • Page 31 — [WS ≥ 8] 0.25 × T − 4.0 WR assertion to data active — –2.4 — [2 ≤ WS ≤ 3] –0.25 × T − 4.0 –5.7 — [WS ≥ 4] DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-11...
  • Page 32 The WS number applies to the access in which the deassertion of WR occurs and assumes the next access uses a minimal number of wait states. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted. DSP56311 Technical Data, Rev. 8 2-12 Freescale Semiconductor...
  • Page 33 Data D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-11. SRAM Write Access DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-13...
  • Page 34 Page mode cycle time for mixed (read and write) accesses 35.0 — 2 × T − 5.7 CAS assertion to data valid (read) — 14.3 3 × T − 5.7 Column address valid to data valid (read) — 24.3 DSP56311 Technical Data, Rev. 8 2-14 Freescale Semiconductor...
  • Page 35 The number of wait states for Page mode access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. The asynchronous delays specified in the expressions are valid for the DSP56311. equals 4 ×...
  • Page 36 The refresh period is specified in the DRAM Control Register. The asynchronous delays specified in the expressions are valid for the DSP56311. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t equals 3 ×...
  • Page 37 Data Out Data Out Figure 2-13. DRAM Page Mode Write Accesses Column Column Last Column A[0–17] Address Address Address D[0–23] Data In Data In Data In Figure 2-14. DRAM Page Mode Read Accesses DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-17...
  • Page 38 − 4.0 CAS deassertion to RAS assertion 53.5 — 4.25 × T CAS deassertion pulse width – 6.0 36.5 — 4.25 × T − 4.0 Row address valid to RAS assertion 38.5 — DSP56311 Technical Data, Rev. 8 2-18 Freescale Semiconductor...
  • Page 39 Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) . Either t or t must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t and not t DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-19...
  • Page 40 Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) . Either t or t must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t and not t DSP56311 Technical Data, Rev. 8 2-20 Freescale Semiconductor...
  • Page 41 AC Electrical Characteristics Row Address Column Address A[0–17] Data D[0–23] Figure 2-16. DRAM Out-of-Page Read Access DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-21...
  • Page 42 Specifications Row Address Column Address A[0–17] D[0–23] Data Out Figure 2-17. DRAM Out-of-Page Write Access Figure 2-18. DRAM Refresh Access DSP56311 Technical Data, Rev. 8 2-22 Freescale Semiconductor...
  • Page 43 DSP56300 component may assume mastership at the same time. Therefore, some non-overlap period between one input active to another input active is required. Timing 251 ensures that overlaps are avoided. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-23...
  • Page 44 10.1 — 5, 7, 8 Register” read 1.5 × T Delay from write data strobe deassertion to host request assertion for “Last Data + 3.5 13.4 — 6, 7, 8 Register” write DSP56311 Technical Data, Rev. 8 2-24 Freescale Semiconductor...
  • Page 45 Register” read or write (HROD=1, open drain host request) Notes: See the Programmer’s Model section in the chapter on the HI08 in the DSP56311 User’s Manual . In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
  • Page 46 HRRQ (double host request) Figure 2-21. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] H[7–0] HREQ (single host request) HRRQ (double host request) Figure 2-22. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe DSP56311 Technical Data, Rev. 8 2-26 Freescale Semiconductor...
  • Page 47 HTRQ (double host request) Figure 2-23. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] H[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-24. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-27...
  • Page 48 Figure 2-25. Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] HAD[7–0] Address Data HREQ (single host request) HRRQ (double host request) Figure 2-26. Read Timing Diagram, Multiplexed Bus, Double Data Strobe DSP56311 Technical Data, Rev. 8 2-28 Freescale Semiconductor...
  • Page 49 Figure 2-27. Write Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] HAD[7–0] Data Address HREQ (single host request) HTRQ (double host request) Figure 2-28. Write Timing Diagram, Multiplexed Bus, Double Data Strobe DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-29...
  • Page 50 SCI clock control register and T = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t is determined by the SCI clock control register and T DSP56311 Technical Data, Rev. 8 2-30 Freescale Semiconductor...
  • Page 51 Data Valid Data Valid a) Internal Clock SCLK (Input) Data Valid Data Valid b) External Clock Figure 2-29. SCI Synchronous Mode Timing 1X SCLK (Output) Data Valid Figure 2-30. SCI Asynchronous Mode Timing DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-31...
  • Page 52 TXC rising edge to FST out (word-length-relative) low — 33.0 x ck — 19.0 i ck TXC rising edge to FST out (word-length) high — 30.0 x ck — 16.0 i ck DSP56311 Technical Data, Rev. 8 2-32 Freescale Semiconductor...
  • Page 53 = internal clock, Asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, Synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-33...
  • Page 54 In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. Figure 2-31. ESSI Transmitter Timing DSP56311 Technical Data, Rev. 8 2-34 Freescale Semiconductor...
  • Page 55 = 3.3 V ± 0.3 V, V = 1.8 V ± 0.1 V; T Note: = –40°C to +100 °C, C = 50 pF CCQH Figure 2-33. TIO Timer Event Input Restrictions DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-35...
  • Page 56 GPIO (Output) GPIO Valid (Input) A[0–17] Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of the GPIO data register. Figure 2-34. GPIO Timing DSP56311 Technical Data, Rev. 8 2-36 Freescale Semiconductor...
  • Page 57 = 1.8 V ± 0.1 V; T Notes: = –40°C to +100 °C, C = 50 pF. CCQH All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor 2-37...
  • Page 58 Output Data Valid Outputs Figure 2-36. Boundary Scan (JTAG) Timing Diagram (Input) Input Data Valid (Input) Output Data Valid (Output) (Output) Output Data Valid (Output) Figure 2-37. Test Access Port Timing Diagram DSP56311 Technical Data, Rev. 8 2-38 Freescale Semiconductor...
  • Page 59 1.5 × T DE assertion time in order to enter Debug mode + 10.0 20.0 — 5.5 × T Response time when DSP56311 is executing NOP instructions from + 30.0 — 67.0 internal memory 3 × T Debug acknowledge assertion time 25.0...
  • Page 60 Specifications DSP56311 Technical Data, Rev. 8 2-40 Freescale Semiconductor...

  • Page 61: Chapter 3 Packaging

    Packaging This section includes diagrams of the DSP56311 package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. The DSP56311 is available in a 196-pin molded array plastic-ball grid array (MAP-BGA) package. DSP56311 Technical Data, Rev. 8...

  • Page 62: Package Description

    SC01 STD0 SRD0 SC10 SC00 CCQH SCK1 SCLK CCQL SCK0 CCQH CCQL HACK HREQ TIO2 TIO1 TIO0 EXTAL CLKOUT BCLK CCQH RESET BCLK CCQL PCAP XTAL Figure 3-1. DSP56311 MAP-BGA Package, Top View DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 63 PINIT SRD0 STD0 SC00 SC10 CCQH SCLK SCK1 CCQL SCK0 CCQL CCQH HACK HREQ TIO2 TIO0 TIO1 EXTAL BCLK CLKOUT CCQH RESET BCLK CCQL XTAL PCAP Figure 3-2. DSP56311 MAP-BGA Package, Bottom View DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 64 STD1 or PD5 MODA/IRQA STD0 or PC5 MODC/IRQC SRD0 or PC4 CCQL SRD1 or PD4 SC12 or PD2 TRST PINIT/NMI MODD/IRQD SC01 or PC1 RXD or PE0 SC10 or PD0 SC00 or PC0 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 65 HTRQ/HTRQ, or PB14 TIO2 CCQH SCK1 or PD3 SCLK or PE2 TXD or PE1 HACK/HACK, HRRQ/HRRQ, or PB15 HRW, HRD/HRD, or PB11 HDS/HDS, HWR/HWR, or PB12 HCS/HCS, HA10, or PB13 TIO1 TIO0 CCQL CCQH CCQL DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 66 Therefore, except for GND and GND that support the PLL, other GND signals do not support individual subsystems in the chip. CLKOUT, BCLK, and BCLK are available only if the operating frequency is ≤ 100 MHz. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 67 Package Description Table 3-2. Signal List by Signal Name Ball Ball Ball Signal Name Signal Name Signal Name CLKOUT EXTAL BCLK BCLK DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 68 Signal List by Signal Name (Continued) Ball Ball Ball Signal Name Signal Name Signal Name HA10 HACK/HACK HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HAS HCS/HCS HDS/HDS HRD/HRD HREQ/HREQ HRRQ/HRRQ HTRQ/HTRQ HWR/HWR DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 69 TRST PINIT RAS0 RAS1 PB10 RAS2 PB11 RAS3 PB12 PB13 RESET PB14 PB15 SC00 SC01 CCQH SC02 CCQH SC10 CCQH SC11 CCQL SC12 CCQL SCK0 CCQL SCK1 CCQL SCLK SRD0 SRD1 STD0 XTAL DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 70: Map-Bga Package Mechanical Drawing

    Packaging 3.2 MAP-BGA Package Mechanical Drawing Figure 3-3. DSP56311 Mechanical Information, 196-pin MAP-BGA Package DSP56311 Technical Data, Rev. 8 3-10 Freescale Semiconductor...

  • Page 71: Design Considerations

    Design Considerations This section describes various areas to consider when incorporating the DSP56311 device into a system design. 4.1 Thermal Design Considerations , in ° C can be obtained from this equation: An estimate of the chip junction temperature, T ×...

  • Page 72: Electrical Design Considerations

    Ensure that capacitor leads and associated printed circuit traces that connect to the chip pins are less than 0.5 inch per capacitor lead. • Use at least a four-layer PCB with two inner layers for DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 73: Power Consumption Considerations

    Designs should minimize this condition to the shortest possible duration. • Ensure that during power-up, and throughout the DSP56311 operation, V is always higher or equal to CCQH the V voltage level.

  • Page 74: Pll Performance Issues

    0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between − 1.4 ns and +3.2 ns. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 75 PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...

  • Page 76: Input (Extal) Jitter Requirements

    (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 77 Power Consumption Benchmark The following benchmark program evaluates DSP56311 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
  • Page 78 ; ebd #60,_end x0,y0,a x:(r0)+,x1 y:(r4)+,y1 x1,y1,a x:(r0)+,x0 y:(r4)+,y0 x0,y0,a x:(r0)+,x1 x1,y1,a y:(r4)+,y0 move b1,x:$ff _end PROG_END XDAT_START $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 79 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540 XDAT_END YDAT_START $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 80 $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 YDAT_END ;************************************************************************** EQUATES for DSP56311 I/O registers and ports Last update: June 11 1995 ;************************************************************************** DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 81 HPCR bits definition M_HGEN EQU $0 ; Host Port GPIO Enable M_HA8EN EQU $1 ; Host Address 8 Enable M_HA9EN EQU $2 ; Host Address 9 Enable M_HCSEN EQU $3 ; Host Chip Select Enable DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 82 ; Idle Line Flag M_OR EQU 4 ; Overrun Error Flag M_PE EQU 5 ; Parity Error M_FE EQU 6 ; Framing Error Flag M_R8 EQU 7 ; Received Bit 8 (R8) Address DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 83 ; Serial Control Direction Mask M_SCD0 EQU 2 ; Serial Control 0 Direction M_SCD1 EQU 3 ; Serial Control 1 Direction M_SCD2 EQU 4 ; Serial Control 2 Direction M_SCKD EQU 5 ; Clock Source Direction DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 84 M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31) ;------------------------------------------------------------------------ EQUATES for Exception Processing ;------------------------------------------------------------------------ Register Addresses M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 85 Interrupt Priority Level (high) M_T0L EQU $300 ; TIMER Interrupt Priority Level Mask M_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low) M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high) ;------------------------------------------------------------------------ EQUATES for TIMER ;------------------------------------------------------------------------ DSP56311 Technical Data, Rev. 8 Freescale Semiconductor...
  • Page 86 EQUATES for Direct Memory Access (DMA) ;------------------------------------------------------------------------ Register Addresses Of DMA M_DSTR EQU FFFFF4 ; DMA Status Register M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0 M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1 DSP56311 Technical Data, Rev. 8 A-10 Freescale Semiconductor...
  • Page 87 M_DAM3 EQU 7 ; DMA Address Mode 3 M_DAM4 EQU 8 ; DMA Address Mode 4 M_DAM5 EQU 9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode DSP56311 Technical Data, Rev. 8 Freescale Semiconductor A-11...
  • Page 88 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 ; XTAL Range select bit M_XTLD EQU 16 ; XTAL Disable Bit M_PSTP EQU 17 ; STOP Processing State Bit M_PEN EQU 18 ; PLL Enable Bit DSP56311 Technical Data, Rev. 8 A-12 Freescale Semiconductor...
  • Page 89 ; Address to Compare Bits Mask (BAC0-BAC11) control and status bits in SR M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow DSP56311 Technical Data, Rev. 8 Freescale Semiconductor A-13...
  • Page 90 M_SEN EQU 20 ; Stack Extension Enable bit in OMR. ;************************************************************************* EQUATES for DSP56311 interrupts Last update: June 11 1995 ;************************************************************************* page 132,55,0,0,0 intequ ident @DEF(I_VEC) ;leave user definition as is. else DSP56311 Technical Data, Rev. 8 A-14 Freescale Semiconductor...
  • Page 91 ; ESSI1 Transmit last slot ;------------------------------------------------------------------------ ; SCI Interrupts ;------------------------------------------------------------------------ I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data DSP56311 Technical Data, Rev. 8 Freescale Semiconductor A-15...
  • Page 92 ; EFCOP Filter Interrupts ;----------------------------------------------------------------------- I_FDIIE I_VEC+$68 ; EFilter input buffer empty I_FDOIE I_VEC+$6A ; EFilter output buffer full ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space DSP56311 Technical Data, Rev. 8 A-16 Freescale Semiconductor...

  • Page 96: Ordering Information

    Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Core Supply Part Package Type Frequency Solder Spheres Order Number Voltage Count (MHz) DSP56311 1.8 V core Molded Array Process-Ball Grid...

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