Timer Prescaler Load Register (Tplr) - Freescale Semiconductor DSP56311 User Manual

Triple Timer Module
23
23
23
15
PCE
7
TC3
23
23
23
Reserved bit. Read as 0. Write with 0 for future compatibility

9.4.2 Timer Prescaler Load Register (TPLR)

The TPLR is a read/write register that controls the prescaler divide factor (that is, the number that
the prescaler counter loads and begins counting from) and the source for the prescaler input
clock.
23 22 21
PS1 PS0
11 10 9
PL11 PL10 PL9
— Reserved bit. Read as 0. Write to 0 for future compatibility
9-22
22 21 20 19
TCF TOF
14 13 12 11
DO DI DIR
6 5 4 3
TC2 TC1 TC0
Figure 9-20. Timer Module Programming Model
20 19
PL20 PL19 PL18
8 7
PL8 PL7
Figure 9-21. Timer Prescaler Load Register (TPLR)
DSP56311 User's Manual, Rev. 2
0
Timer Prescaler Load
Register (TPLR)
TPLR = $FFFF83
0
Timer Prescaler Count
Register (TPCR)
TPLR = $FFFF82
18 17 16
Timer Control/Status
Register (TCSR)
10 9 8
TCSR0 = $FFFF8F
TCSR1 = $FFFF8B
TRM
INV
TCSR2 = $FFFF87
2 1 0
TCIE TOIE TE
0
Timer Load
Register (TLR)
TLR0 = $FFFF8E
TLR1 = $FFFF8A
TLR2 = $FFFF86
0
Timer Compare
Register (TCPR)
TCPR0 = $FFFF8D
TCPR1 = $FFFF89
TCPR2 = $FFFF85
0
Timer Count
Register (TCR)
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
18 17 16
PL17 PL16
6 5 4
PL6 PL5 PL4
15 14 13
PL15 PL14 PL13
3 2 1
PL3 PL2 PL1
Freescale Semiconductor
12
PL12
0
PL0