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Table 7-6 summarizes the ESSI port signal configurations.
PCRC/PCRD[i]
1
0
0
X: The signal setting is irrelevant to the Port Signal[i] function.
7.6.3 Port Data Registers (PDRC and PDRD)
Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal
lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is configured as an
input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value present on the input
signal line. If a port signal PC[i] or PD[i] is configured as an output (GPO), a value written to the
corresponding PDRC[i] pr PDRD[i] bit is reflected as a value on the output signal line. Either a
hardware
signal or a software RESET instruction clears all PDRC and PDRD bits.
RESET
23
22
11
10
Note:
For bits 5–0, the value represents the level that is written to or read from the associated signal line if it is
enabled as a GPIO signal by the respective port control register (PCRC or PCRD) bits. For ESSI0, the GPIO
signals are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding data bits for Port C
GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD)
Freescale Semiconductor
Table 7-6. ESSI Port Signal Configurations
PRRC/PRRD[i]
X
0
1
21
20
19
9
8
7
DSP56311 User's Manual, Rev. 2
Port Signal[i] Function
Port C/Port D GPI
Port C/Port D GPO
18
17
16
6
5
4
PDRx5
PDRx4
PDRx3
GPIO Signals and Registers
ESSI0/ESSI1
15
14
13
3
2
1
PDRx2
PDRx1
12
0
PDRx0
7-35
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