Ground; Clock; Pll - Freescale Semiconductor DSP56311 User Manual

Signals/Connections

2.2 Ground

Ground Name
GND PLL Ground— A ground dedicated for PLL use. The connection should be provided with an extremely low-impedance
P
path to ground. V
package.
GND PLL Ground 1—A ground dedicated for PLL use. The connection should be provided with an extremely low-impedance
P1
path to ground.
GND Ground—Connected to an internal device ground plane. The user must provide adequate external decoupling
capacitors for all GND connections

2.3 Clock

Signal State During
Type
Name
EXTAL Input Input
XTAL Output Chip-driven

2.4 PLL

Signal Name Type
PCAP Input
CLKOUT Output
2-4
Table 2-3. Grounds
should be bypassed to GND
CCP
Table 2-4. Clock Signals
Reset
External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an
external crystal or an external clock.
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
Table 2-5. Phase-Lock Loop Signals
State During
Reset
Input PLL Capacitor—Connects an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP is tied to V
Chip-driven Clock Output—Provides an output clock synchronized to the internal
core clock phase.
If the PLL is enabled and both the multiplication and division factors
equal one, then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of
EXTAL.
Note: At operating frequencies above 100 MHz, this signal produces a
low-amplitude waveform that is not usable externally by other devices.
Above 100 MHz, you use the asynchronous bus arbitration option that is
enabled by the Asynchronous Bus Arbitration Enable (ABE) bit in the
Operating Mode Register (OMR). When set, the DSP enters the
Asynchronous Arbitration mode, which eliminates the BB and BG setup
and hold time requirements with respect to CLKOUT.
DSP56311 User's Manual, Rev. 2
Description
by a 0.47 µF capacitor located as close as possible to the chip
P
Signal Description
Signal Description
CCP
, GND, or left floating.
CC
Freescale Semiconductor
.