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10.4 EFCOP Programming Model
This section documents the registers for configuring and operating the EFCOP. The EFCOP
registers available to the DSP programmer are listed in Table 10-5. The following paragraphs
describe these registers in detail.
Address
Y:$FFFFB0
Y:$FFFFB1
Y:$FFFFB2
Y:$FFFFB3
Y:$FFFFB4
Y:$FFFFB5
Y:$FFFFB6
Y:$FFFFB7
Y:$FFFFB8
Note: The EFCOP registers are mapped onto Y data memory space.
10.4.1 Filter Data Input Register (FDIR)
The FDIR is a 4-word deep, 24-bit wide FIFO for DSP-to-EFCOP data transfers. Up to four data
samples can be written into the FDIR at the same address. Data from the FDIR is transferred to
the FDM for filter processing. For proper operation, write data to the FDIR only if the FDIBE
status bit is set, indicating that the FIFO is empty. A write to the FDIR clears the FDIBE bit. Data
transfers can be triggered by an interrupt request (for core transfers) or a DMA request (for DMA
transfers). The FDIR is accessible for writes by the DSP56300 core and the DMA controller.
10.4.2 Filter Data Output Register (FDOR)
The FDOR is a 24-bit read-only register for EFCOP-to-DSP data transfers. The result of the filter
processing is transferred from the FMAC to the FDOR. For proper operation, read data from the
FDOR only if the FDOBF status bit is set, indicating that the FDOR contains data. A read from
the FDOR clears the FDOBF bit. Data transfers can be triggered by an interrupt request (for core
transfers) or a DMA request (DMA transfers). The FDOR is accessible for reads by the
DSP56300 core and the DMA controller.
Freescale Semiconductor
Table 10-5. EFCOP Registers and Base Addresses
DSP56311 Reference Manual, Rev. 2
EFCOP Register Name
Filter data input register (FDIR)
Filter data output register (FDOR)
Filter K-constant register (FKIR)
Filter count register (FCNT)
Filter control status register (FCSR)
Filter ALU control register (FACR)
Filter data buffer base address (FDBA)
Filter coefficient base address (FCBA)
Filter decimation/channel register (FDCH)
EFCOP Programming Model
10-35
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