Host Data Register (Hdr); Host Base Address Register (Hbar) - Freescale Semiconductor DSP56311 User Manual

6.6.4 Host Data Register (HDR)

The HDR register holds the data value of the corresponding bits of the HI08 signals configured as
GPIO signals. The functionality of Dxx depends on the corresponding HDDR bit (that is,
DRxx).The host processor can not access the Host Data Register (HDR)
15 14 13
D15 D14 D13
HDDR
DRxx
0 Read-only bit—The value read is the binary value of
the signal. The corresponding signal is configured as
an input.
1 Read/write bit— The value written is the value read.
The corresponding signal is configured as an output
and is driven with the data written to Dxx.
1. Defined by the selected configuration.

6.6.5 Host Base Address Register (HBAR)

In multiplexed bus modes, HBAR selects the base address where the host-side registers are
mapped into the host bus address space. The address from the host bus is compared with the base
address as programmed in the Base Address Register. An internal chip select is generated if a
match is found. Figure 6-11 shows how the chip-select logic uses HBAR.
15 14 13
—Reserved bit, read as 0, write to 0 for future compatibility.
Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)
Table 6-11. Host Base Address Register (HBAR) Bit Definitions
Bit Number Bit Name
15–8
7–0 BA[10–3]
Freescale Semiconductor
12 11 10 9
D12 D11 D10 D9
Figure 6-9. Host Data Register (HDR) (X:$FFFFC8)
Table 6-10. HDR and HDDR Functionality
1
GPIO Signal
12 11 10 9
Reset Value
0 Reserved. Write to 0 for future compatibility.
$80 Base Address
Reflect the base address where the host-side registers are mapped into
the bus address space.
DSP56311 User's Manual, Rev. 2
8 7 6 5
D8 D7 D6 D5
HDR
D xx
Read-only bit—Does not contain significant data.
Read/write bit— The value written is the value read.
8 7 6 5
BA10 BA9 BA8
Description
DSP Core Programming Model
4 3 2 1
D4 D3 D2 D1
1
Non-GPIO Signal
4 3 2 1
BA7 BA6 BA5 BA4
0
D0
0
BA3
6-15